MC68306 Integrated EC000 Processor User's Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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(c) MOTOROLA, 1993 PREFACE The complete documentation package for the MC68306 consists of the MC68306UM/AD, MC68306 EC000 Integrated Processor User's Manual, M68000PM/AD, MC68000 Family Programmer's Reference Manual, and the MC68306P/D, MC68306 EC000 Integrated Processor Product Brief. The MC68306 EC000 Integrated Processor User's Manual describes the programming, capabilities, registers, and operation of the MC68306; the MC68000 Family Programmer's Reference Manual provides instruction details for the MC68306; and the MC68306 EC000 Integrated Processor Product Brief provides a brief description of the MC68306 capabilities. This user's manual is organized as follows: Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Section 8 Section 9 Introduction Signal Descriptions 68000 Bus Operation Description EC000 Core Processor System Operation Serial Module IEEE 1149.1 Test Access Port Electrical Specifications Ordering Information and Mechanical Data 68K FAX-IT - Documentation Comments FAX 512-891-8593--Documentation Comments Only The Motorola High-End Technical Publications Department provides a fax number for you to submit any questions or comments about this document or how to order other documents. We welcome your suggestions for improving our documentation. Please do not fax technical questions. Please provide the part number and revision number (located in upper right-hand corner of the cover) and the title of the document. When referring to items in the manual, please reference by the page number, paragraph number, figure number, table number, and line number if needed. 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Applications and Technical Information For questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. -- Sales Offices -- UNITED STATES ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA, Los Angeles CALIFORNIA, Irvine CALIFORNIA, Rosevllle CALIFORNIA, San Diego CALIFORNIA, Sunnyvale COLORADO , Colorado Springs COLORADO , Denver CONNECTICUT, Wallingford FLORIDA , Maitland FLORIDA , Pompano Beach/ Fort Lauderdale FLORIDA , Clearwater GEORGlA , Atlanta IDAHO , Boise ILLINOIS , Chicago/Hoffman Estates INDlANA, Fort Wayne INDIANA, Indianapolis INDIANA, Kokomo IOWA , Cedar Rapids KANSAS , Kansas City/Mission MARYLAND , Columbia MASSACHUSETTS, Marborough MASSACHUSETTS, Woburn MICHIGAN, Detroit MINNESOTA, Minnetonka MISSOURI , St. Louis NEW JERSEY, Fairfield NEW YORK, Fairport NEW YORK, Hauppauge NEW YORK, Poughkeepsie/Fishkill NORTH CAROLINA , Raleigh OHIO, Cleveland OHIO, Columbus Worthington OHIO, Dayton OKLAHOMA, Tulsa OREGON , Portland PENNSYLVANIA , Colmar Philadelphia/Horsham TENNESSEE, Knoxville TEXAS , Austin TEXAS , Houston TEXAS , Plano VIRGINIA , Richmond WASHINGTON , Bellevue Seattle Access WISCONSIN, Milwaukee/Brookfield (205) 464-6800 (602) 897-5056 (818) 706-1929 (310) 417-8848 (714) 753-7360 (916) 922-7152 (619) 541-2163 (408) 749-0510 (719) 599-7497 (303) 337-3434 (203) 949-4100 (407) 628-2636 (305) 486-9776 (813) 538-7750 (404) 729-7100 (208) 323-9413 (708) 490-9500 (219) 436-5818 (317) 571-0400 (317) 457-6634 (319) 373-1328 (913) 451-8555 (410) 381-1570 (508) 481-8100 (617) 932-9700 (313) 347-6800 (612) 932-1500 (314) 275-7380 (201) 808-2400 (716) 425-4000 (516) 361-7000 (914) 473-8102 (919) 870-4355 (216) 349-3100 (614) 431-8492 (513) 495-6800 (800) 544-9496 (503) 641-3681 (215) 997-1020 (215) 957-4100 (615) 690-5593 (512) 873-2000 (800) 343-2692 (214) 516-5100 (804) 285-2100 (206) 454-4160 (206) 622-9960 (414) 792-0122 FINLAND, Helsinki Car Phone FRANCE, Paris/Vanves GERMANY , Langenhagen/ Hanover GERMANY , Munich GERMANY , Nuremberg GERMANY , Sindelfingen GERMANY ,Wiesbaden HONG KONG, Kwai Fong Tai Po INDIA , Bangalore ISRAEL, Tel Aviv ITALY, Milan JAPAN, Aizu JAPAN, Atsugi JAPAN, Kumagaya JAPAN, Kyushu JAPAN, Mito JAPAN, Nagoya JAPAN, Osaka JAPAN, Sendai JAPAN, Tachikawa JAPAN, Tokyo JAPAN, Yokohama KOREA , Pusan KOREA , Seoul MALAYSIA , Penang MEXICO , Mexico City MEXICO , Guadalajara Marketing Customer Service NETHERLANDS, Best PUERTO RICO , San Juan SINGAPORE SPAIN, Madrid or SWEDEN, Solna SWITZERLAND, Geneva SWITZERLAND, Zurich TAlWAN , Taipei THAILAND , Bangkok UNITED KINGDOM , Aylesbury 358-0-35161191 358(49)211501 33(1)40 955 900 49(511)789911 49 89 92103-0 49 911 64-3044 49 7031 69 910 49 611 761921 852-4808333 852-6668333 (91-812)627094 972(3)753-8222 39(2)82201 81(241)272231 81(0462)23-0761 81(0485)26-2600 81(092)771-4212 81(0292)26-2340 81(052)232-1621 81(06)305-1801 81(22)268-4333 81(0425)23-6700 81(03)3440-3311 81(045)472-2751 82(51)4635-035 82(2)554-5188 60(4)374514 52(5)282-2864 52(36)21-8977 52(36)21-9023 52(36)669-9160 (31)49988 612 11 (809)793-2170 (65)2945438 34(1)457-8204 34(1)457-8254 46(8)734-8800 41(22)7991111 41(1)730 4074 886(2)717-7089 (66-2)254-4910 44(296)395-252 FULL LINE REPRESENTATIVES COLORADO , Grand Junction Cheryl Lee Whltely KANSAS , Wichita Melinda Shores/Kelly Greiving NEVADA , Reno Galena Technology Group NEW MEXICO, Albuquerque S&S Technologies, lnc. UTAH, Salt Lake City Utah Component Sales, Inc. WASHINGTON , Spokane Doug Kenley ARGENTINA , Buenos Aires Argonics, S.A. (303) 243-9658 (316) 838 0190 (702) 746 0642 (505) 298-7177 (801) 561-5099 (509) 924-2322 (541) 343-1787 Field Applications Engineering Available Through All Sales Offices CANADA BRITISH COLUMBIA, Vancouver ONTARIO , Toronto ONTARIO , Ottawa QUEBEC, Montreal (604) 293-7605 (416) 497-8181 (613) 226-3491 (514) 731-6881 HYBRID COMPONENTS RESELLERS Elmo Semiconductor Minco Technology Labs Inc. Semi Dice Inc. (818) 768-7400 (512) 834-2022 (310) 594-4631 INTERNATIONAL AUSTRALIA, Melbourne AUSTRALIA, Sydney BRAZIL, Sao Paulo CHINA, Beijing (61-3)887-0711 (61(2)906-3855 55(11)815-4200 86 505-2180 TABLE OF CONTENTS Paragraph Number Title Section 1 Introduction 1.1 MC68EC000 Core processor.................................................................................. 1-2 1.2 On-Chip Peripherals ............................................................................................... 1-3 1.2.1 Serial Module ....................................................................................................... 1-3 1.2.2 DRAM Controller .................................................................................................. 1-4 1.2.3 Chip Selects......................................................................................................... 1-4 1.2.4 Parallel Ports........................................................................................................ 1-4 1.2.5 Interrupt Controller ............................................................................................... 1-4 1.2.6 Clock .................................................................................................................... 1-5 1.2.7 Bus Timeout Monitor ............................................................................................ 1-5 1.2.8 Mode Controller ................................................................................................... 1-5 1.2.9 IEEE 1149.1 Test................................................................................................. 1-5 Section 2 Signal Descriptions 2.1 Bus Signals ............................................................................................................. 2-5 2.1.1 Address Bus (A23-A1) ........................................................................................ 2-5 2.1.2 Address Strobe (AS) ............................................................................................ 2-5 2.1.3 Bus Error (BERR ) ................................................................................................ 2-5 2.1.4 Bus Request (BR) ................................................................................................ 2-5 2.1.5 Bus Grant (BG ) .................................................................................................... 2-6 2.1.6 Bus Grant Acknowledge (BGACK) ....................................................................... 2-6 2.1.7 Data Bus (D15-D0) ............................................................................................. 2-6 2.1.8 Data Transfer Acknowledge (DTACK) ................................................................. 2-6 2.1.9 DRAM Multiplexed Address Bus (DRAMA14 -DRAMA0) ..................................... 2-6 2.1.10 Processor Function Codes (FC2-FC0).............................................................. 2-6 2.1.11 Halt (HALT) ........................................................................................................ 2-7 2.1.12 Read/Write (R/W) ............................................................................................... 2-7 2.1.13 Upper And Lower Data Strobes (UDS , LDS ) ..................................................... 2-7 2.1.14 Upper Byte Write (UW ) ...................................................................................... 2-8 2.1.15 Lower Byte Write (LW )....................................................................................... 2-8 2.1.16 Output Enable (OE) ........................................................................................... 2-8 2.1.17 Reset (RESET ) .................................................................................................. 2-8 2.2 Chip Select Signals................................................................................................. 2-9 Page Number MOTOROLA MC68306 USER'S MANUAL v TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number 2.3 DRAM Controller Signals........................................................................................ 2-9 2.3.1 Column Address Strobe (CAS1-CAS0 )............................................................... 2-9 2.3.2 Row Address Strobe (RAS1 -RAS0) .................................................................... 2-9 2.3.3 DRAM Write Signal (DRAMW) ............................................................................. 2-9 2.4 Interrupt Control and Parallel Port Signals ............................................................. 2-9 2.4.1 Interrupt Request (IRQ7-IRQ1) ........................................................................... 2-9 2.4.2 Interrupt Acknowledge (IACK7-IACK1) ............................................................... 2-9 2.4.3 Port A Signals (PA7-PA0) ................................................................................... 2-9 2.4.4 Port B (PB7-PB0) ................................................................................................ 2-9 2.5 Clock and Mode Control Signals ............................................................................ 2-10 2.5.1 Crystal Oscillator (EXTAL, XTAL) ........................................................................ 2-10 2.5.2 Clock Out (CLKOUT) ........................................................................................... 2-10 2.5.3 Address Mode (AMODE) ..................................................................................... 2-10 2.6 Serial Module Signals ............................................................................................. 2-10 2.6.1 Channel A Receiver Serial-Data Input (RxDA) .................................................... 2-10 2.6.2 Channel A Transmitter Serial-Data Output (TxDA) ............................................. 2-10 2.6.3 Channel B Receiver Serial-Data Input (RxDB) .................................................... 2-10 2.6.4 Channel B Transmitter Serial-Data Output (TxDB) ............................................. 2-10 2.6.5 CTSA ................................................................................................................... 2-11 2.6.6 RTSA ................................................................................................................... 2-11 2.6.7 CTSB ................................................................................................................... 2-11 2.6.8 RTSB ................................................................................................................... 2-11 2.6.9 Crystal Oscillator (X1, X2) ................................................................................... 2-11 2.6.10 IP2 ..................................................................................................................... 2-11 2.6.11 OP3 ................................................................................................................... 2-11 2.7 JTAG Port Test Signals .......................................................................................... 2-11 2.7.1 Test Clock (TCK) ................................................................................................. 2-12 2.7.2 Test Mode Select (TMS)...................................................................................... 2-12 2.7.3 Test Data In (TDI) ................................................................................................ 2-12 2.7.4 Test Data Out (TDO) ........................................................................................... 2-12 2.7.5 Test Reset (TRST) .............................................................................................. 2-12 Section 3 68000 Bus Operation Description 3.1 Data Transfer Operations ....................................................................................... 3-1 3.1.1 Read Cycle .......................................................................................................... 3-1 3.1.2 Write Cycle .......................................................................................................... 3-4 3.1.3 Read-Modify-Write Cycle..................................................................................... 3-7 3.1.4 CPU Space Cycle ................................................................................................ 3-11 vi MC68306 USER'S MANUAL MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number 3.2 Bus Arbitration ........................................................................................................ 3-12 3.2.1 Requesting the Bus ............................................................................................. 3-15 3.2.2 Receiving the Bus Grant ...................................................................................... 3-16 3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only) ............................ 3-16 3.3 Bus Arbitration Control ............................................................................................ 3-16 3.4 Bus Error and Halt Operation ................................................................................. 3-24 3.4.1 Bus Error Operation ............................................................................................. 3-24 3.4.2 Retrying the Bus Cycle ........................................................................................ 3-25 3.4.3 Halt Operation...................................................................................................... 3-26 3.4.4 Double Bus Fault ................................................................................................. 3-27 3.5 Reset Operation...................................................................................................... 3-28 3.6 The Relationship of DTACK, BERR , and HALT ...................................................... 3-28 3.7 Asynchronous Operation ........................................................................................ 3-30 3.8 Synchronous Operation .......................................................................................... 3-33 Section 4 EC000 Core Processor 4.1 Features.................................................................................................................. 4-1 4.2 Processing States ................................................................................................... 4-1 4.3 Programming Model ............................................................................................... 4-2 4.3.1 Data Format Summary......................................................................................... 4-3 4.3.2 Addressing Capabilities Summary ....................................................................... 4-4 4.3.3 Notation Conventions .......................................................................................... 4-5 4.4 EC000 Core Instruction Set Overview .................................................................... 4-7 4.5 Exception Processing ............................................................................................. 4-12 4.5.1 Exception Vectors ................................................................................................ 4-14 4.6 Processing of Specific Exceptions .......................................................................... 4-16 4.6.1 Reset Exception................................................................................................... 4-17 4.6.2 Interrupt Exceptions ............................................................................................. 4-17 4.6.3 Uninitialized Interrupt Exception .......................................................................... 4-18 4.6.4 Spurious Interrupt Exception................................................................................ 4-18 4.6.5 Instruction Traps .................................................................................................. 4-18 4.6.6 Illegal and Unimplemented Instructions ............................................................... 4-18 4.6.7 Privilege Violations............................................................................................... 4-19 4.6.8 Tracing ................................................................................................................. 4-19 4.6.9 Bus Error .............................................................................................................. 4-20 4.6.10 Address Error ..................................................................................................... 4-21 4.6.11 Multiple Exceptions ............................................................................................ 4-21 MOTOROLA MC68306 USER'S MANUAL vii TABLE OF CONTENTS (Continued) Paragraph Number Title Section 5 System Operation 5.1 MC68306 Address Space ....................................................................................... 5-1 5.2 Register Description ............................................................................................... 5-3 5.2.1 System Register .................................................................................................. 5-3 5.2.2 Timer Vector Register .......................................................................................... 5-4 5.2.3 Bus Timeout Period Register............................................................................... 5-4 5.2.4 Interrupt Registers ............................................................................................... 5-5 5.2.4.1 Interrupt Control Register ................................................................................. 5-5 5.2.4.2 Interrupt Status Register................................................................................... 5-6 5.2.5 I/O Port Registers ................................................................................................ 5-6 5.2.5.1 Port Pins Register ............................................................................................. 5-7 5.2.5.2 Port Direction Register ..................................................................................... 5-7 5.2.5.3 Port Data Register ............................................................................................ 5-8 5.2.6 Chip Selects......................................................................................................... 5-8 5.2.6.1 Chip Select Configuration Registers (High Half) .............................................. 5-9 5.2.6.2 Chip Select Configuration Registers (Low Half) ............................................... 5-10 5.2.7 DRAM Control Registers ..................................................................................... 5-12 5.2.7.1 DRAM Refresh Register ................................................................................... 5-13 5.2.7.2 DRAM Bank Configuration Register (High Half) ............................................... 5-14 5.2.7.3 DRAM Bank Configuration Register (Low Half) ................................................ 5-14 5.2.8 Automatic DTACK Generation............................................................................. 5-16 5.3 Crystal Oscillator .................................................................................................... 5-16 Section 6 Serial Module 6.1 Module Overview .................................................................................................... 6-2 6.1.1 Serial Communication Channels A and B............................................................ 6-3 6.1.2 Baud Rate Generator Logic ................................................................................. 6-3 6.1.3 Timer/Counter ...................................................................................................... 6-3 6.1.4 Interrupt Control Logic ......................................................................................... 6-3 6.1.5 Comparison of Serial Module to MC68681.......................................................... 6-4 6.2 Serial Module Signal Definitions ............................................................................. 6-4 6.2.3 Channel A Transmitter Serial Data Output (TxDA).............................................. 6-4 6.2.4 Channel A Receiver Serial Data Input (RxDA) .................................................... 6-5 6.2.5 Channel B Transmitter Serial Data Output (TxDB).............................................. 6-5 6.2.6 Channel B Receiver Serial Data Input (RxDB) .................................................... 6-6 6.2.7 Channel A Request-To-Send (RTSA/OP0) ......................................................... 6-6 6.2.7.1 RTSA ................................................................................................................ 6-6 6.2.7.2 OP0 .................................................................................................................. 6-6 6.2.8 Channel B Request-To-Send (RTSB/OP1) ......................................................... 6-6 Page Number viii MC68306 USER'S MANUAL MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number 6.2.8.1 RTSB ................................................................................................................ 6-6 6.2.8.2 OP1................................................................................................................... 6-6 6.2.9 Channel A Clear-To-Send (CTSA/IP0) ................................................................ 6-6 6.2.9.1 CTSA ................................................................................................................ 6-6 6.2.9.2 IP0 .................................................................................................................... 6-6 6.2.10 Channel B Clear-To-Send (CTSB/IP1) .............................................................. 6-6 6.2.10.1 CTSB .............................................................................................................. 6-6 6.2.10.2 IP1 .................................................................................................................. 6-6 6.3 Operation ................................................................................................................ 6-7 6.3.1 Baud Rate Generator........................................................................................... 6-7 6.3.2 Transmitter and Receiver Operating Modes ........................................................ 6-7 6.3.2.1 Transmitter ........................................................................................................ 6-9 6.3.2.2 Receiver............................................................................................................ 6-10 6.3.2.3 FIFO Stack ........................................................................................................ 6-11 6.3.3 Looping Modes .................................................................................................... 6-13 6.3.3.1 Automatic Echo Mode....................................................................................... 6-13 6.3.3.2 Local Loopback Mode....................................................................................... 6-13 6.3.3.3 Remote Loopback Mode ................................................................................... 6-13 6.3.4 Multidrop Mode .................................................................................................... 6-14 6.3.5 Counter/Timer ...................................................................................................... 6-16 6.3.5.1 Counter Mode ................................................................................................... 6-16 6.3.5.2 Timer Mode....................................................................................................... 6-16 6.3.6 Bus Operation ...................................................................................................... 6-17 6.3.6.1 Read Cycles ................................................................................................ ..... 6-17 6.3.6.2 Write Cycles...................................................................................................... 6-17 6.3.6.3 Interrupt Acknowledge Cycles .......................................................................... 6-17 6.4 Register Description and Programming .................................................................. 6-17 6.4.1 Register Description ............................................................................................ 6-17 6.4.1.1 Mode Register 1 (DUMR1) ............................................................................... 6-18 6.4.1.2 Mode Register 2 (DUMR2) ............................................................................... 6-20 6.4.1.3 Status Register (DUSR).................................................................................... 6-22 6.4.1.4 Clock-Select Register (DUCSR) ....................................................................... 6-24 6.4.1.5 Command Register (DUCR) ............................................................................. 6-26 6.4.1.6 Receiver Buffer (DURB) ................................................................................... 6-29 6.4.1.7 Transmitter Buffer (DUTB) ................................................................................ 6-29 6.4.1.8 Input Port Change Register (DUIPCR) ............................................................. 6-29 6.4.1.9 Auxiliary Control Register (DUACR) ................................................................ 6-30 6.4.1.10 Interrupt Status Register (DUISR) .................................................................. 6-31 6.4.1.11 Interrupt MASK Register (DUIMR).................................................................. 6-33 6.4.1.12 Count Register Current MSB of Counter (DUCUR) ........................................ 6-33 6.4.1.13 Count Register Current LSB of Counter (DUCLR) ......................................... 6-33 6.4.1.14 Counter/Timer Upper Preload Register (CTUR) ............................................. 6-34 MOTOROLA MC68306 USER'S MANUAL ix TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number 6.4.1.15 Counter/Timer Lower Pimer Register (CTLR) ................................................ 6-34 6.4.1.16 Interrupt Vector Register (DUIVR) .................................................................. 6-34 6.4.1.17 Input Port Register .......................................................................................... 6-34 6.4.1.18 Output Port Control Register (DUOPCR) ....................................................... 6-35 6.4.1.19 Output Port Data Register (DUOP) ................................................................ 6-35 6.4.1.20 Start Counter Command Register .................................................................. 6-36 6.4.1.21 Stop Counter Command Register .................................................................. 6-36 6.4.2 Programming ....................................................................................................... 6-36 6.4.2.1 Serial Module Initialization. ............................................................................... 6-36 6.4.2.2 I/O Driver Example ........................................................................................... 6-37 6.4.2.3 Interrupt Handling ............................................................................................. 6-37 6.5 Serial Module Initialization Sequence ..................................................................... 6-43 Section 7 IEEE 1149.1 Test Access Port 7.1 Overview................................................................................................................. 7-1 7.2 TAP Controller ........................................................................................................ 7-3 7.3 Boundary Scan Register......................................................................................... 7-3 7.4 Instruction Register................................................................................................. 7-9 7.4.1 EXTEST (000) ................................................................................................ ..... 7-10 7.4.2 SAMPLE/PRELOAD (110) .................................................................................. 7-10 7.4.3 BYPASS (010, 101, 111) ..................................................................................... 7-11 7.4.4 CLAMP (011) ...................................................................................................... 7-11 7.5 MC68306 Restrictions ............................................................................................ 7-11 7.6 Non-IEEE 1149.1 Operation ................................................................................... 7-12 Section 8 Electrical Specifications 8.1 Maximum Ratings ................................................................................................... 8-1 8.2 Thermal Characteristics .......................................................................................... 8-1 8.3 Power Considerations............................................................................................. 8-2 8.4 AC Electrical Specification Definitions .................................................................... 8-2 8.5 DC Electrical Specifications .................................................................................... 8-4 8.6 AC Electrical Specifications--Clock Timing............................................................ 8-4 8.7 AC Electrical Specifications--Read and Write ....................................................... 8-5 8.8 AC Electrical Specifications--Chip Selects ............................................................ 8-9 8.9 AC Electrical Specifications--Bus Arbitration ......................................................... 8-10 8.10 Bus Operation--DRAM Accesses AC Timing Specifications ............................... 8-12 8.11Serial Module Electrical Characteristics ................................................................ 8-15 8.12 Serial Module AC Electrical Characteristics--Clock Timing ................................. 8-16 8.13 AC Electrical Characteristics--Port Timing .......................................................... 8-16 8.14 AC Electrical Characteristics--Interrupt Reset ..................................................... 8-16 x MC68306 USER'S MANUAL MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Number Title Page Number 8.14 AC Electrical Characteristics--Interrupt Reset ..................................................... 8-16 8.15 AC Electrical Characteristics--Transmitter Timing ............................................... 8-17 8.16 AC Electrical Characteristics--Receiver Timing ................................................... 8-18 8.17 IEEE 1149.1 Electrical Characteristics ................................................................. 8-19 Section 9 Ordering Information and Mechanical Data 9.1 Standard Ordering Information ............................................................................... 9-1 9.2 Pin Assignments ..................................................................................................... 9-2 MOTOROLA MC68306 USER'S MANUAL xi LIST OF ILLUSTRATIONS Figure Number Title Page Number Figure 1-1. MC68306 Simplified Block Diagram....................................................... 1-1 Figure 2-1. MC68306 Detailed Block Diagram ......................................................... 2-2 Figure 3-1. Word Read Cycle Flowchart .................................................................. 3-2 Figure 3-2. Byte Read Cycle Flowchart .................................................................... 3-2 Figure 3-3. Read and Write Cycle Timing Diagram .................................................. 3-3 Figure 3-4. Word and Byte Read Cycle Timing Diagram ......................................... 3-3 Figure 3-5. Word Write Cycle Flowchart ................................................................... 3-5 Figure 3-6. Byte Write Cycle Flowchart .................................................................... 3-6 Figure 3-7. Word and Byte Write Cycle Timing Diagram.......................................... 3-6 Figure 3-8. Read-Modify-Write Cycle Flowchart ....................................................... 3-8 Figure 3-9. Read-Modify-Write Cycle Timing Diagram ............................................. 3-9 Figure 3-10. Interrupt Acknowledge Cycle ............................................................... 3-11 Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram ..................................... 3-12 Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart ........................................ 3-13 Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart ........................................... 3-14 Figure 3-14. Three-Wire Bus Arbitration Timing Diagram ........................................ 3-15 Figure 3-15. Two-Wire Bus Arbitration Timing Diagram ........................................... 3-15 Figure 3-16. External Asynchronous Signal Synchronization ................................... 3-17 Figure 3-17. Bus Arbitration Unit State Diagrams..................................................... 3-19 Figure 3-18. Three-Wire Bus Arbitration Timing Diagram--Processor Active .......... 3-20 Figure 3-19. Three-Wire Bus Arbitration Timing Diagram--Bus Inactive ................. 3-21 Figure 3-20. Three-Wire Bus Arbitration Timing Diagram--Special Case ............... 3-22 Figure 3-21. Two-Wire Bus Arbitration Timing Diagram--Processor Active ............ 3-23 Figure 3-22. Two-Wire Bus Arbitration Timing Diagram--Bus Inactive .................... 3-24 Figure 3-23. Two-Wire Bus Arbitration Timing Diagram--Special Case .................. 3-25 Figure 3-24. Bus Error Timing Diagram .................................................................... 3-26 Figure 3-25. Retry Bus Cycle Timing Diagram ......................................................... 3-27 Figure 3-26. Halt Operation Timing Diagram............................................................ 3-28 Figure 3-27. Reset Operation Timing Diagram......................................................... 3-29 Figure 3-28 Fully Asynchronous Read Cycle ........................................................... 3-32 Figure 3-29. Fully Asynchronous Write Cycle........................................................... 3-32 Figure 3-30. Pseudo-Asynchronous Read Cycle ..................................................... 3-33 Figure 3-31. Pseudo-Asynchronous Write Cycle...................................................... 3-34 Figure 3-32. Synchronous Read Cycle..................................................................... 3-36 Figure 3-33. Synchronous Write Cycle ..................................................................... 3-37 xii MC68306 USER'S MANUAL MOTOROLA LIST OF ILLUSTRATIONS (Continued) Figure Number Title Page Number Figure 4-1. Programmer's Model .............................................................................. 4-2 Figure 4-2. Status Register ....................................................................................... 4-3 Figure 4-3. General Exception Processing Flowchart .............................................. 4-13 Figure 4-4. General Form of Exception Stack Frame ............................................... 4-14 Figure 4-5. Exception Vector Format ........................................................................ 4-15 Figure 4-6. Address Translated from 8-Bit Vector Number ...................................... 4-15 Figure 4-7. Supervisor Stack Order for Bus or Address Error Exception ................. 4-21 Figure 5-1. Chip Select Expansion ........................................................................... 5-12 Figure 5-2. Oscillator Circuit Diagram....................................................................... 5-17 Figure 6-1. Simplified Block Diagram ....................................................................... 6-1 Figure 6-2. External and Internal Interface Signals .................................................. 6-5 Figure 6-3. Baud Rate Generator Block Diagram ..................................................... 6-7 Figure 6-4. Transmitter and Receiver Functional Diagram ....................................... 6-8 Figure 6-5. Transmitter Timing Diagram ................................................................... 6-9 Figure 6-6. Receiver Timing Diagram ....................................................................... 6-11 Figure 6-7. Looping Modes Functional Diagram ....................................................... 6-14 Figure 6-8. Multidrop Mode Timing Diagram ............................................................ 6-15 Figure 6-9. Serial Module Programming Model ........................................................ 6-18 Figure 6-10. Serial Module Programming Flowchart ................................................ 6-38 Figure 7-1. Test Access Port Block Diagram ............................................................ 7-2 Figure 7-2. TAP Controller State Machine ................................................................ 7-3 Figure 7-3. Output Cell (O.Cell) ................................................................................ 7-7 Figure 7-4. Input Cell (I.Cell) ..................................................................................... 7-7 Figure 7-5. Output Control Cell (En.Cell) .................................................................. 7-8 Figure 7-6. Bidirectional Cell (IO.Cell) ...................................................................... 7-8 Figure 7-7. Bidirectional Cell (IOx0.Cell)................................................................... 7-9 Figure 7-8. General Arrangement for Bidirectional Pins ........................................... 7-9 Figure 7-9. Bypass Register ..................................................................................... 7-11 Figure 8-1. Drive Levels and Test Points for AC Specifications ............................... 8-3 Figure 8-2. Clock Output Timing ............................................................................... 8-4 Figure 8-3. Read Cycle Timing Diagram................................................................... 8-7 Figure 8-4. Write Cycle Timing Diagram ................................................................... 8-8 Figure 8-5. Chip Select and Interrupt Acknowledge Timing Diagram ....................... 8-9 Figure 8-6. Bus Arbitration Timing Diagram ............................................................. 8-10 Figure 8-7. Bus Arbitration Timing Diagram ............................................................. 8-11 Figure 8-8. DRAM Timing - 0-Wait Read, No Refresh ............................................. 8-13 Figure 8-9. DRAM Timing - 1-Wait Write, No Refresh ............................................. 8-14 Figure 8-10. DRAM Timing - 0- and 1-Wait Refresh ................................................ 8-14 MOTOROLA MC68306 USER'S MANUAL xiii LIST OF ILLUSTRATIONS (Continued) Figure Number Title Page Number Figure 8-11. DRAM Timing - 1-Wait, Test and Set .................................................. 8-15 Figure 8-12. Clock Timing......................................................................................... 8-16 Figure 8-13. Port Timing ........................................................................................... 8-16 Figure 8-14. Interrupt Reset Timing .......................................................................... 8-17 Figure 8-15. Transmit Timing ................................................................................... 8-17 Figure 8-16. Receive Timing .................................................................................... 8-18 Figure 8-17. Test Clock Input Timing Diagram ......................................................... 8-19 Figure 8-18. Boundary Scan Timing Diagram .......................................................... 8-20 Figure 8-19. Test Access Port Timing Diagram ........................................................ 8-20 xiv MC68306 USER'S MANUAL MOTOROLA LIST OF TABLES Table Number Title Page Number Table 2-1. Bus Signal Summary ............................................................................... 2-3 Table 2-2. Chip Select Signal Summary ................................................................... 2-3 Table 2-3. DRAM Controller Signal Summary .......................................................... 2-3 Table 2-4. Interrupt and Parallel Port Signal Summary ............................................ 2-4 Table 2-5. Clock and Mode Control Signal Summary............................................... 2-4 Table 2-6. Serial Module Signal Summary ............................................................... 2-4 Table 2-7. JTAG Signal Summary ............................................................................ 2-5 Table 2-8. Function Code Outputs ............................................................................ 2-7 Table 2-9. Data Strobe Control of Data Bus ............................................................. 2-8 Table 3-1. DTACK, BERR, and HALT Assertion Results ......................................... 3-24 Table 3-2. BERR and HALT Negation Results ......................................................... 3-25 Table 4-1. Processor Data Formats.......................................................................... 4-3 Table 4-2. Effective Addressing Modes .................................................................... 4-4 Table 4-3. Notation Conventions .............................................................................. 4-5 Table 4-4. EC000 Core Instruction Set Summary .................................................... 4-8 Table 4-5. Exception Vector Assignments ................................................................ 4-16 Table 4-6. Exception Grouping and Priority .............................................................. 4-22 Table 5-1. MC68306 Memory Map ........................................................................... 5-2 Table 5-2. Chip Select Match Bits ............................................................................ 5-11 Table 5-3. DRAM Address Multiplexer...................................................................... 5-13 Table 5-4. DRAM Bank Match Bits ........................................................................... 5-15 Table 6-1. PMx and PT Control Bits ......................................................................... 6-20 Table 6-2. B/Cx Control Bits ..................................................................................... 6-20 Table 6-3. CMx Control Bits...................................................................................... 6-21 Table 6-4. SBx Control Bits ...................................................................................... 6-22 Table 6-5. RCSx Control Bits.................................................................................... 6-25 Table 6-6. TCSx Control Bits .................................................................................... 6-26 Table 6-7. MISCx Control Bits .................................................................................. 6-27 Table 6-8. TCx Control Bits ...................................................................................... 6-28 Table 6-9. RCx Control Bits ...................................................................................... 6-28 Table 6-10. Counter/Timer Mode and Source Select Bits ........................................ 6-30 MOTOROLA MC68306 USER'S MANUAL xv LIST OF TABLES (Continued) Table Number Title Page Number Table 7-1. Boundary Scan Control Bits .................................................................... 7-4 Table 7-2. Boundary Scan Bit Definitions ................................................................. 7-5 Table 7-3. Instructions .............................................................................................. 7-10 xvi MC68306 USER'S MANUAL MOTOROLA SECTION 1 INTRODUCTION The MC68306 is an integrated processor containing an MC68EC000 processor and elements common to many MC68000- and MC68EC000-based systems. Designers of virtually any application requiring MC68000-class performance will find that the MC68306 reduces design time by providing valuable system elements integrated in one chip. The combination of peripherals offered in the MC68306 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing. Systems requiring serial communication and dynamic random access memory (DRAM) can especially benefit from using the MC68306. The MC68306's high level of functional integration results in significant reductions in component count, power consumption, board space, and cost while yielding much higher system reliability and shorter design time. Complete code compatibility with the MC68000 affords the designer access to a broad base of established real-time kernels, operating systems, languages, applications, and development tools, many of which are oriented towards embedded control. Figure 1-1 shows a simplified block diagram of the MC68306. 8 DRAM CONTROLLER PORT A EC000 CORE PROCESSOR 8 CHIP SELECTS INTERRUPT CONTROLLER CLOCK MODE CONTROLLER JTAG PORT PORT B 24 16 16-BIT TIMER TWO-CHANNEL SERIAL I/O 8 Figure 1-1. MC68306 Simplified Block Diagram MOTOROLA MC68306 USER'S MANUAL 1-1 The primary features of the MC68306 are as follows: * Functional Integration on a Single Piece of Silicon * EC000 Core--Identical to MC68EC000 Microprocessor -- Complete Code Compatibility with MC68000 and MC68EC000 -- High Performance--2.4 MIPS -- Extended Internal Address Range - to 4 Gbyte * Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (DUART) -- Baud Rate Generators -- Modem Control -- Compatible with MC68681/MC2681 -- Integrated 16-Bit Timer/Counter * DRAM Controller -- Supports up to 16 Mbytes using 4M x 1 DRAMs, 64 Mbytes using 16M x 1 DRAMs -- Provides Zero Wait State Interface to 80-ns DRAMs -- Programmable Refresh Timer Provides CAS -before-RAS Refresh * Chip Selects -- Eight Programmable Chip Select Signals -- Provide Eight Separate 1-Mbyte Spaces or Four Separate 16-Mbyte Spaces -- Programmable Wait States * Programmable Interrupt Controller * Bus Timeout * 24 Address Lines, 16 Data Lines * 16.67 MHz, 5 Volt Operation * 144-Pin Thin Quad Flat Pack (TQFP)or 132-Pin Plastic Quad Flat Pack (PQFP) 1.1 MC68EC000 CORE PROCESSOR The MC68EC000 is a core implementation of the MC68000 32-bit microprocessor architecture. The programmer can use any of the eight 32-bit data registers for fast manipulation of data and any of the eight 32-bit address registers for indexing data in memory. Flexible instructions support data movement, arithmetic functions, logical operations, shifts and rotates, bit set and clear, conditional and unconditional program branches, and overall system control. The MC68EC000 core can operate on data types of single bits, binary-coded decimal (BCD) digits, and 8, 16, and 32 bits. The integrated chip selects allow peripherals and data in memory to reside anywhere in the 4-Gbyte linear address space. A supervisor operating mode protects system-level resources from the more restricted user mode, allowing a true virtual environment to be developed. Many addressing modes complement 1-2 MC68306 USER'S MANUAL MOTOROLA these instructions, including predecrement and postincrement, which allow simple stack and queue maintenance and scaled indexing for efficient table accesses. Data types and addressing modes are supported orthogonally by all data operations and with all appropriate addressing modes. Position-independent code is easily written. Like all M68000 family processors, the MC68EC000 core recognizes interrupts of seven different priority levels and allows either an automatic vector or a peripheral-supplied vector to direct the processor to the desired service routine. Internal trap exceptions ensure proper instruction execution with good addresses and data, allow operating system intervention in special situations, and permit instruction tracing. Hardware signals can either terminate or rerun bad memory accesses before instructions process data incorrectly. The EC000 core provides 2.4 MIPS at 16.67 MHz. 1.2 ON-CHIP PERIPHERALS To improve total system throughput and reduce part count, board size, and cost of system implementation, the M68300 family integrates on-chip, intelligent peripheral modules and typical glue logic. The functions on the MC68306 include two serial channels, a timer/counter, a DRAM controller, a parallel port, and system glue logic. 1.2.1 Serial Module Most digital systems use serial I/O to communicate with host computers, operator terminals, or remote devices. The MC68306 contains a two-channel, full-duplex UART with an integrated timer. An on-chip baud rate generator provides standard baud rates up the 38.4K baud to each channel's receiver and transmitter. The serial module is identical to the MC68681/MC2681 DUART. Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. Each channel provides a wide variety of error detection and maskable interrupt capability. Full-duplex, autoecho loopback, local loopback, and remote loopback modes can be selected. Multidrop applications are also supported. A 3.6864 MHz crystal drives the baud rate generators. Each transmit and receive channel can be programmed for a different baud rate. Full modem support is provided with separate request-to-send (RTS) and clear-to-send (CTS) signals for each channel. The integrated 16-bit timer/counter can operate in a counter mode or a timer mode. The timer/counter can function as a system stopwatch, a real-time single interrupt generator, or a device watchdog when in counter mode. In timer mode, the timer/counter can be used as a programmable clock source for channels A and B, a periodic interrupt generator, or a variable duty cycle square-wave generator. 1.2.2 DRAM Controller DRAM is used in many systems since it is the least expensive form of high-speed storage available. However, considerable design effort is often spent designing the interface MOTOROLA MC68306 USER'S MANUAL 1-3 between the processor and DRAM. The MC68306 contains a full DRAM controller, greatly reducing design time and complexity. The DRAM controller provides row address strobe (RAS) and column address strobe (CAS) signals for two separate banks of DRAMs. Each bank can include up to 16 devices; up to 15 multiplexed address lines are also available. Thus, using 4M x 1 DRAMs, up to 16 Mbytes of DRAM are supported; with 16M x 1 DRAMs, up to 64 Mbytes of DRAM are supported. A programmable refresh timer provides CAS-before- RAS refreshes at designated intervals. The DRAM controller has its own address registers that control the address range selected by each RAS and CAS signal, leaving the eight integrated chip selects free for other system peripherals. DRAM accesses are zero wait states using 80-ns DRAMs. 1.2.3 Chip Selects The MC68306 provides up to eight programmable chip select outputs, in most cases eliminating the need for external address decoding. All handshaking and timing signals are provided, with up to 950-ns access times. Each chip select can access a 16 Mbyte address space located anywhere in the 4-Gbyte address range. Internal registers allow the base address, range, and cycle duration of each chip select to be independently programmed. After reset, chip select (CS0) responds to all accesses until the chip selects have been properly programmed. Four of the chip selects are multiplexed with the most significant address bits (A23-A20). The address mode (AMODE) input determines the functions of these outputs. 1.2.4 Parallel Ports Two 8-bit parallel ports are provided. The port pins can be individually programmed to be inputs or outputs. If the pins are programmed to be inputs, the value on those pins can be read by accessing an on-board register. If the pins are programmed to be outputs, the pins will reflect the value programmed into another on-board register. The port B pins are multiplexed with four interrupt request and four interrupt acknowledge lines. The function of these pins is controlled by the internal registers. 1.2.5 Interrupt Controller Seven input signals are provided to trigger an external interrupt, one for each of the seven priority levels supported. Each input can be programmed to be active high or active low. Seven separate outputs indicate the priority level of the interrupt being serviced. Interrupts at each priority level can be pre-programmed to go to the default service routine. For maximum flexibility, interrupts can be vectored to the correct service routine by the interrupting device. 1.2.6 Clock To save on system costs, the MC68306 has an on-board oscillator that can be driven with a 16.67-MHz crystal. A bus clock output is provided by a CLKOUT pin. Alternatively, an 1-4 MC68306 USER'S MANUAL MOTOROLA external 16.67-MHz oscillator can be used, with a tight skew between the input clock signal and the bus clock on the CLKOUT pin. 1.2.7 Bus Timeout Monitor A bus timeout monitor is provided to automatically terminate and report as erroneous any bus cycle that is not normally terminated after a pre-programmed length of time. The user can program this timeout period to be up to 4096 clocks. 1.2.8 IEEE 1149.1 Test To aid in system diagnostics, the MC68306 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group). MOTOROLA MC68306 USER'S MANUAL 1-5 SECTION 2 SIGNAL DESCRIPTION This section contains a brief description of the input and output signals, with reference (if applicable) to other sections which give greater detail on its use. Figure 2-1 provides a detailed diagram showing the integrated peripherals and signals, and Tables 2-1-2-7 provides a quick reference for determining a signal's name, mnemonic, its use as an input or output, active state, and type identification. NOTE The terms assertion and negation will be used extensively. This is done to avoid confusion when dealing with a mixture of "active low" and "active high" signals. The term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. The term negate or negation is used to indicate that a signal is inactive or false. MOTOROLA MC68306 USER'S MANUAL 2-1 DRAMW RAS1 RAS0 CAS1 CAS0 EXTAL XTAL CLKOUT AMODE CS0 CS1 CS2 CS3 CS4/A20 CS5/A21 CS6/A22 CS7/A23 CHIP SELECTS DRAM CONTROLLER A19-A16 A15/DRAMA14-A1/DRAMA0 D15-D0 CLOCK MODE CONTROLLER FC2-FC0 RESET BERR HALT AS UDS LDS R/W UW LW OE DTACK BR BG BGACK TCK TMS TDI TDO TRST IRQ7 IRQ4 IRQ1 IACK7 IACK4 IACK1 IRQ6/PB7 IRQ5/PB6 IRQ3/PB5 IRQ2/PB4 IACK6/PB3 IACK5/PB2 IACK3/PB1 IACK2/PB0 EC000 CORE PROCESSOR JTAG PORT INTERRUPT CONTROLLER PORT B PORT A 16-BIT TIMER/ COUNTER TWOCHANNEL SERIAL I/O X2 X1/CLK RxDA TxDA RxDB TxDB FLOW CONTROL RTSB/OP1 RTSA/OP0 CTSB/IP1 CTSA/IP0 Figure 2-1. MC68306 Detailed Block Diagram PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 OP3 IP2 2-2 MC68306 USER'S MANUAL MOTOROLA Table 2-1. Bus Signal Summary Signal Name Address Signals Address Strobe Bus Error Bus Grant Bus Grant Acknowledge Bus Request Data Bus Data Transfer Acknowledge DRAM Multiplexed Address14-0 Function Codes Halt Lower Data Strobe Upper Data Strobe Lower-Byte Write Strobe Upper-Byte Write Strobe Output Enable Read/Write Reset NOTES: 1. Pullup may be required, value depends on individual application. Must not be left floating. Mnemonic A23-A1 AS BERR BG BGACK BR D15-D0 DTACK DRAMA14-DRAMA0 FC2-FC0 HALT LDS UDS LW UW OE R/ W RESET Input/ Output Output Output I/O Output Input Input I/O I/O Output Output I/O I/O I/O Output Output Output Output I/O Three-State During Bus Arbitration Yes Yes -- No -- -- Yes -- Yes Yes -- Yes Yes No No No Yes -- 2.2 K 2.2 K 4.7 K 4.7 K 2.2 K (1) (1) 4.7 K 2.2 K Pullup Required Table 2-2. Chip Select Signal Summary Signal Name Chip Select Chip Select 4-7/Address Port 23 - 20 Mnemonic CS3-CS0 CS7-CS4/ A23-A20 Input/ Output Output Output Three-State During Bus Arbitration Yes Yes Pullup Required 4.7 K 4.7 K Table 2-3. DRAM Controller Signal Summary Signal Name Column Address Strobe Row Address Strobe DRAM Write Signal Mnemonic CAS1-CAS0 RAS1-RAS0 DRAMW Input/ Output Output Output Output Three-State During Bus Arbitration Yes Yes Yes Pullup Required 4.7 K 4.7 K MOTOROLA MC68306 USER'S MANUAL 2-3 Table 2-4. Interrupt and Parallel Port Signal Summary Signal Name Interrupt Request Level 7, 4, 1 Interrupt Request Level 6/Port B 7 Interrupt Request Level 5/Port B 6 Interrupt Request Level 3/Port B 5 Interrupt Request Level 2/Port B 4 Interrupt Acknowledge 7, 4, 1 Interrupt Acknowledge 6/Port B 7 Interrupt Acknowledge 5/Port B 6 Interrupt Acknowledge 3/Port B 5 Interrupt Acknowledge 2/Port B 4 Port A Mnemonic IRQ7, IRQ4, IRQ1 IRQ6/PB7 IRQ5/PB6 IRQ3/PB5 IRQ2/PB4 IACK7, IACK4, IACK1 IACK6 /PB3 IACK5 /PB2 IACK3 /PB1 IACK2 /PB0 PA7-PA0 Input/ Output Input I/O I/O I/O I/O Output I/O I/O I/O I/O I/O Three-State During Bus Arbitration -- -- -- -- -- -- -- -- -- -- -- (2) (2) (2) (2) (2) Pullup Required (2) (2) (2) (2) (2) NOTES: 2. Pullup or pulldown may be required, value depends on individual application. Table 2-5. Clock and Mode Control Signal Summary Signal Name Crystal Oscillator or External Clock Crystal Oscillator System Clock Address Mode Mnemonic EXTAL XTAL CLKOUT AMODE Input/ Output Input Output Output Input Three-State During Bus Arbitration -- -- No -- Pullup Required 2-4 MC68306 USER'S MANUAL MOTOROLA Table 2-6. Serial Module Signal Summary Signal Name Channel A Receiver Serial Data Channel A Transmitter Serial Data Channel B Receiver Serial Data Channel B Transmitter Serial Data Channel A Clear-to-Send Channel A Request-to-Send Channel B Clear-to-Send Channel B Request-to-Send Crystal Output Crystal Input or External Clock Parallel Input 2 Parallel Output 3 NOTES: 1. Pullup may be required, value depends on individual application. Must not be left floating. Mnemonic RxDA TxDA RxDB TxDB CTSA /IP0 RTSA /OP0 CTSB /IP1 RTSB /OP1 X2 X1/CLK IP2 OP3 Input/ Output Input Output Input Output Input Output Input Output Output Input Input Output Three-State During Bus Arbitration -- No -- No -- No -- No No -- -- No (1) (1) (1) Pullup Required Table 2-7. JTAG Signal Summary Signal Name Test Clock Test Data Input Test Data Output Test Mode Select Test Reset NOTES: 3. Pin has internal pullup, but external pulldown may be required for correct initialization. Mnemonic TCK TDI TDO TMS TRST Input/ Output Input Input Output Input Input Three-State During Bus Arbitration -- -- -- -- -- 4.7 K (3) Pulldown Required 2.1 BUS SIGNALS The following signals are used for the MC68306 bus. 2.1.1 Address Bus (A23-A1) This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data. This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3 provide the level number of the interrupt being acknowledged, and address lines A23-A4 MOTOROLA MC68306 USER'S MANUAL 2-5 are driven to logic high. A23-A20 are only available in address mode (AMODE=0). A15- A1 are multiplexed with DRAM address. 2.1.2 Address Strobe (AS) Assertion of this three-state signal indicates that the information on the address bus is a valid address. 2.1.3 Bus Error (BERR) Assertion of this bi-directional, open-drain signal indicates a problem in the current bus cycle. The MC68306 can assert this signal to terminate a bus cycle when no external response is received. An external source can assert BERR to indicate a problem such as: 1. No response from a device 2. No interrupt vector number returned 3. An illegal access request rejected by a memory management unit 4. Some other application-dependent error Either the processor retries the bus cycle or performs exception processing, as determined by interaction between the bus error signal and the halt signal. 2.1.4 Bus Request (BR) This input can be wire-ORed with bus request signals from all other devices that could be bus masters. Assertion of this signal indicates to the processor that some other device needs to become the bus master. Bus requests can be issued at any time during a bus cycle or between cycles. 2.1.5 Bus Grant (BG ) This output signal indicates to all other potential bus master devices that the processor will relinquish bus control at the end of the current bus cycle. 2.1.6 Bus Grant Acknowledge (BGACK ) Assertion of this input indicates that some other device has become the bus master. This signal should not be asserted until the following conditions are met: 1. A bus grant has been received. 2. Address strobe is inactive, which indicates that the microprocessor is not using the bus. 3. Data transfer acknowledge is inactive, which indicates that neither memory nor peripherals are using the bus. 4. Bus grant acknowledge is inactive, which indicates that no other device is claiming bus mastership. 2-6 MC68306 USER'S MANUAL MOTOROLA BGACK can be negated (pulled high), and the MC68306 will operate in a two-wire bus arbitration system. 2.1.7 Data Bus (D15-D0) This bi-directional, three-state bus is the general-purpose data path. It is 16 bits wide and can transfer and accept data of either word or byte length. During an interrupt acknowledge cycle, an external device can supply the interrupt vector number on data lines D7-D0. 2.1.8 Data Transfer Acknowledge (DTACK ) Assertion of this bi-directional, open-drain signal indicates the completion of the data transfer. When the processor recognizes DTACK during a read cycle, data is latched, and the bus cycle is terminated. When DTACK is recognized during a write cycle, the bus cycle is terminated. The MC68306 generates DTACK for all internal cycles, DRAM cycles, and autovector IACK cycles, and can be programmed to generate DTACK for any chip select cycle. (Refer to 3.7 Asynchronous Operation and 3.8 Synchronous Operation.) 2.1.9 DRAM Multiplexed Address Bus (DRAMA14-DRAMA0) These signals provide fifteen multiplexed address bits used during row address strobe. 2.1.10 Processor Function Codes (FC2-FC0) These function code outputs indicate the mode (user or supervisor) and the address space type currently being accessed, as shown in Table 2-8. The function code outputs are valid whenever AS is asserted. Table 2-8. Function Code Outputs Function Code Output FC2 Low Low Low Low High High High High FC1 Low Low High High Low Low High High FC0 Low High Low High Low High Low High Address Space Type (Undefined, Reserved) User Data User Program (Undefined, Reserved) (Undefined, Reserved) Supervisor Data Supervisor Program CPU Space 2.1.11 Halt (HALT) External assertion of this bi-directional signal causes the processor to stop bus activity at the completion of the bus cycle for which the input met set-up time requirements (i.e., current or next cycle). This operation places all control signals in the inactive state. For MOTOROLA MC68306 USER'S MANUAL 2-7 additional information about the interaction between HALT and RESET , refer to 3.5 Reset Operation and for more information on HALT and BERR , refer to 3.4 Bus Error and Halt Operation. Processor assertion of HALT indicates a double bus fault condition. This condition is unrecoverable; the MC68306 must be externally reset to resume operation. 2.1.12 Read/Write (R/W) This three-state, bi-directional signal defines the data bus transfer as a read or write cycle. The R/W signal relates to the data strobe signals described in the following paragraphs. 2.1.13 Upper And Lower Data Strobes (UDS , LDS) These three-state, bi-directional signals and R/W control the flow of data on the data bus. Table 2-9 lists the combinations of these signals, the corresponding data on the bus, and the OE, LW, and UW signals. When the R/W line is high, the processor reads from the data bus. When the R/W line is low, the processor drives the data bus. When another bus master controls the bus, the UDS, LDS, and R/ W pins become inputs and the OE, LW, and UW signals are still decoded as shown in Table 2-9. Table 2-9. Data Strobe Control of Data Bus UDS High Low High Low Low High Low LDS High Low Low High Low Low High R/ W -- High High High Low Low Low D8-D15 No Valid Data Valid Data Bits 15-8 No Valid Data Valid Data Bits 15-8 Valid Data Bits 15-8 Valid Data Bits 7-0* Valid Data Bits 15-8 D0-D7 No Valid Data Valid Data Bits 7-0 Valid Data Bits 7-0 No Valid Data Valid Data Bits 7-0 Valid Data Bits 7-0 Valid Data Bits 15-8* OE High Low Low Low High High High UW High High High High Low High Low LW High High High High Low Low High *These conditions are a result of current implementation and may not appear on future devices. 2.1.14 Upper-Byte Write (UW ) This signal is a combination of R/W low and UDS low for writing the upper-byte of a 16-bit port. This signal simplifies memory system design by explicitly signalling that data is valid on the upper portion of the data bus on a write operation. UW is also decoded for external bus masters. 2-8 MC68306 USER'S MANUAL MOTOROLA 2.1.15 Lower-Byte Write (LW ) This signal is a combination of R/W low and LDS low for writing the lower-byte of a 16-bit port. This signal simplifies memory system design by explicitly signalling that data is valid on the lower portion of the data bus on a write operation. LW is also decoded for external bus masters. 2.1.16 Output Enable (OE) OE is a combination of R/ W high and an active data strobe (UDS or LDS ). OE is also decoded for external bus masters. 2.1.17 Reset (RESET ) The external assertion of this bi-directional, open-drain signal can start a system initialization sequence by resetting the processor. The processor assertion of RESET (from executing a RESET instruction) resets all external devices of a system without affecting the internal state of the processor. The interaction of internal and external RESET , and the HALT signal is described in paragraph 3.5 Reset Operation. 2.2 CHIP SELECT SIGNALS These eight three-state signals provide address decodes with programmable base and range. CS7 -CS4 are only available in chip select mode (AMODE bit =1). CS3-CS0 are always available. 2.3 DRAM CONTROLLER SIGNALS The following signals are used to control an external DRAM for the MC68306. 2.3.1 Column Address Strobe (CAS1 -CAS0 ) These three-state signals provide column address strobe timing for external DRAM. CAS0 controls data lines D15-D8 and CAS1 controls D7-D0. 2.3.2 Row Address Strobe (RAS1 -RAS0 ) These three-state signals provide row address strobe timing for external DRAM. Each RAS controls a separate bank of DRAM. 2.3.3 DRAM Write Signal (DRAMW ) This signal provides write control for external DRAM. 2.4 INTERRUPT CONTROL AND PARALLEL PORT SIGNALS The following signals are used for interrupt control on the MC68306. MOTOROLA MC68306 USER'S MANUAL 2-9 2.4.1 Interrupt Request (IRQ7-IRQ1) Three input signals (IRQ7, IRQ4, IRQ1) notify the core processor of an interrupt request. Four additional interrupt request lines (IRQ6, IRQ5, IRQ3, and IRQ2) are shared with parallel port B pins and may be individually programmed as interrupts. 2.4.2 Interrupt Acknowledge (IACK7 -IACK1 ) Three output signals (IACK7, IACK4, IACK1 ) indicate an interrupt acknowledge cycle. Four additional interrupt acknowledge lines (IACK6, IACK5, IACK3, and IACK2) are shared with parallel port B pins and may be individually programmed as interrupt acknowledges. 2.4.3 Port A Signals (PA7-PA0) These eight pins serve as port A parallel input/output signals. 2.4.4 Port B (PB7-PB0) These eight pins are shared with IRQ6, IRQ5, IRQ3, IRQ2 and IACK6, IACK5, IACK3, IACK2, and can be individually programmed to serve as port B parallel input/output signals. 2.5 CLOCK AND MODE CONTROL SIGNALS These four pins are used to connect an external crystal to the on-chip oscillator and define the four multifunction pins. 2.5.1 Crystal Oscillator (EXTAL, XTAL) These two pins are the connections for an external crystal to the internal oscillator circuit. If an external oscillator is used, it should be connected to EXTAL, with XTAL left open, and must drive CMOS levels. A crystal or clock input must be supplied at all times. 2.5.2 Clock Out (CLKOUT) This output signal is the system clock output and is used as the bus timing reference by external devices. 2.5.3 Address Mode (AMODE) This input signal provides mode control for the multi-function chip select pins. When set to zero, A23-A20 is selected and when set to one, CS7-CS4 is selected. The mode selection is static: AMODE is latched at the end of any system reset. 2.6 SERIAL MODULE SIGNALS The following paragraphs describe the signals used by the serial module on the MC68306. 2-10 MC68306 USER'S MANUAL MOTOROLA 2.6.1 Channel A Receiver Serial-Data Input (RxDA) This signal is the receiver serial-data input for channel A. The least-significant bit is received first. Data on this pin is sampled on the rising edge of the programmed clock source. 2.6.2 Channel A Transmitter Serial-Data Output (TxDA) This signal is the transmitter serial-data output for channel A. The least-significant bit is transmitted first. This output is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. (Mark is high and space is low). Data is shifted out this pin on the falling edge of the programmed clock source. 2.6.3 Channel B Receiver Serial-Data Input (RxDB) This signal is the receiver serial-data input for channel B. The least-significant bit is received first. Data on this pin is sampled on the rising edge of the programmed clock source. 2.6.4 Channel B Transmitter Serial-Data Output (TxDB) This signal is the transmitter serial-data output for channel B. The least-significant bit is transmitted first. This output is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out of this pin on the falling edge of the programmed clock source. 2.6.5 CTSA This input can be used as the channel A clear-to-send active low input (CTSA) or general purpose input (IP0). A change-of-state detector is also associated with this input. 2.6.6 RTSA This output can be used as the channel A active low request-to-send (RTSA) output, or a general-purpose output (OP0). When used as RTSA, it is automatically negated and reasserted by either the receiver or transmitter. 2.6.7 CTSB This input can be used as the channel B clear-to-send active low input (CTSB) or general purpose input. A change-of-state detector is also associated with this input. 2.6.8 RTSB This output can be used as a general-purpose output or the channel B active low requestto-send (RTSB) output. When used for this function, it is automatically negated and reasserted by either the receiver or transmitter. MOTOROLA MC68306 USER'S MANUAL 2-11 2.6.9 Crystal Oscillator (X1/CLK, X2) These two pins are the connections for an external crystal to the internal oscillator circuit. If an external oscillator is used, it should be connected to X1/CLK, with X2 left floating, and must drive CMOS levels. A crystal or clock input must be supplied at all times. 2.6.10 IP2 This input can be used as a general-purpose input, the channel B receiver external clock input (RxCB), or the counter/timer external clock input. When this input is used as the external clock by the receiver, the received data is sampled on the rising edge of the clock. A change-of-state detector is also associated with this input. 2.6.11 OP3 This output can be used as a general-purpose output, the open-drain active low counterready output, the open-drain timer output, the channel B transmitter 1X-clock output, or the channel B receiver 1X-clock output. 2.7 JTAG PORT TEST SIGNALS The following signals are used with the on-chip test logic defined by the IEEE 1149.1 standard. See IEEE 1149.1 Test Access Port for more information on the use of these signals. 2.7.1 Test Clock (TCK) This input provides a clock for on-chip test logic defined by the IEEE 1149.1 standard. 2.7.2 Test Mode Select (TMS) This input controls test mode operations for on-chip test logic defined by the IEEE 1149.1 standard. Connecting TMS to V CC disables the test controller, making all JTAG circuits transparent to the system. 2.7.3 Test Data In (TDI) This input is used for serial test instructions and test data for on-chip test logic defined by the IEEE 1149.1 standard. 2.7.4 Test Data Out (TDO) This output is used for serial test instructions and test data for on-chip test logic defined by the IEEE 1149.1 standard. 2.7.5 Test Reset (TRST ) This input is the master reset for on-chip test logic defined by the IEEE 1149.1 standard. 2-12 MC68306 USER'S MANUAL MOTOROLA SECTION 3 68000 BUS OPERATION DESCRIPTION This section describes control signal and bus operation during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. NOTE The terms assertion and negation are used extensively in this manual to avoid confusion when describing a mixture of "active-low" and "active-high" signals. The term assert or assertion is used to indicate that a signal is active or true, independently of whether that level is represented by a high or low voltage. The term negate or negation is used to indicate that a signal is inactive or false. 3.1 DATA TRANSFER OPERATIONS Transfer of data between devices involves the following signals: 1. Address bus A1 through A31 2. Data bus D0 through D7 and/or D8 through D15 3. Control signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. In all cases, the bus master must deskew all signals it issues at both the start and end of a bus cycle. In addition, the bus master must deskew the acknowledge and data signals from the slave device. The following paragraphs describe the read, write, read-modify-write, and CPU space cycles. The indivisible read-modify-write cycle implements interlocked multiprocessor communications. A CPU space cycle is a special processor cycle. 3.1.1 Read Cycle During a read cycle, the processor receives either one or two bytes of data from the memory or from a peripheral device. If the instruction specifies a word or long-word operation, the processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes. A long-word read is accomplished by two consecutive word reads. When the instruction specifies byte operation, the processor uses the internal A0 bit to determine which byte to read and issues the appropriate data strobe. When A0 is zero, the upper data strobe is issued; when A0 is one, the lower data strobe is issued. When the data is received, the processor internally positions the byte appropriately. MOTOROLA MC68306 USER'S MANUAL 3-1 The word read cycle flowchart is shown in Figure 3-1. The byte read cycle flowchart is shown in Figure 3-2. The read and write cycle timing is shown in Figure 3-3. Figure 3-4 shows the word and byte read cycle timing diagram. BUS MASTER ADDRESS THE DEVICE 1) 2) 3) 4) 5) SET R/W TO READ PLACE FUNCTION CODE ON FC2-FC0 PLACE ADDRESS ON ADDRESS BUS ASSERT ADDRESS STROBE (AS) ASSERT UPPER DATA STROBE (UDS) AND LOWER DATA STROBE (LDS) SLAVE OUTPUT THE DATA 1) DECODE ADDRESS 2) PLACE DATA ON D15-D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) ACQUIRE THE DATA 1) LATCH DATA 2) NEGATE UDS AND LDS 3) NEGATE AS TERMINATE THE CYCLE 1) REMOVE DATA FROM D15-D0 2) NEGATE DTACK START NEXT CYCLE Figure 3-1. Word Read Cycle Flowchart BUS MASTER ADDRESS THE DEVICE 1) 2) 3) 4) 5) SET R/W TO READ PLACE FUNCTION CODE ON FC2-FC0 PLACE ADDRESS ON ADDRESS BUS ASSERT ADDRESS STROBE (AS) ASSERT UPPER DATA STROBE (UDS) OR LOWER DATA STROBE (LDS) (BASED ON A0) SLAVE OUTPUT THE DATA 1) DECODE ADDRESS 2) PLACE DATA ON D7-D0 OR D15-D8 (BASED ON UDS OR LDS) 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) ACQUIRE THE DATA 1) LATCH DATA 2) NEGATE UDS AND LDS 3) NEGATE AS TERMINATE THE CYCLE 1) REMOVE DATA FROM D7-D0 OR D15-D8 2) NEGATE DTACK START NEXT CYCLE Figure 3-2. Byte Read Cycle Flowchart 3-2 MC68306 USER'S MANUAL MOTOROLA S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 w CLK FC2-FC0 A31-A1 AS UDS LDS R/W DTACK D15-D8 D7-D0 ww w S5 S6 S7 READ WRITE 2 WAIT STATE READ Figure 3-3. Read and Write Cycle Timing Diagram S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 CLK FC2-FC0 A31-A1 A0 * AS UDS LDS R/W DTACK D15-D8 D7-D0 READ WRITE READ *Internal Signal Only Figure 3-4. Word and Byte Read Cycle Timing Diagram MOTOROLA MC68306 USER'S MANUAL 3-3 A bus cycle consists of eight states. The various signals are asserted during specific states of a read cycle as follows: STATE 0 The read cycle starts in state 0 (S0). The processor places valid function codes on FC0-FC2, a valid address on the bus, and drives R/W high to identify a read cycle. During state 1 (S1), no bus signals are altered. On the rising edge of state 2 (S2), the processor asserts AS and UDS/LDS . During state 3 (S3), no bus signals are altered. During state 4 (S4), the processor waits for a cycle termination signal (DTACK or BERR ). If neither termination signal is asserted before the falling edge at the end of S4, the processor inserts wait states (full clock cycles) until either DTACK or BERR is asserted. Case 1: DTACK received, with or without BERR . STATE 5 STATE 6 STATE 7 During state 5 (S5), no bus signals are altered. Sometime between state 2 (S2) and state 6 (S6), data from the device is driven onto the data bus. On the falling edge of the clock entering state 7 (S7), the processor latches data from the addressed device and negates AS and UDS , LDS . The device negates DTACK or BERR at this time. Case 2: BERR received without DTACK . STATE 5 STATE 6 STATE 7 STATE 8 STATE 9 During state 5 (S5), no bus signals are altered. During state 6 (S6), no bus signals are altered. During state 7 (S7), no bus signals are altered. During state 8 (S8), no bus signals are altered. AS and UDS/LDS negated. Slave negates BERR. STATE 1 STATE 2 STATE 3 STATE 4 3.1.2 Write Cycle During a write cycle, the processor sends bytes of data to the memory or peripheral device. If the instruction specifies a word or long-word operation, the processor issues both UDS and LDS and writes both bytes. A long-word write is accomplished by two consecutive word writes. When the instruction specifies a byte operation, the processor uses the internal A0 bit to determine which byte to write and issues the appropriate data 3-4 MC68306 USER'S MANUAL MOTOROLA strobe. When the A0 bit equals zero, UDS is asserted; when the A0 bit equals one, LDS is asserted. The word write cycle flowchart is shown in Figure 3-5. The byte write cycle flowchart is shown in Figure 3-6. The word and byte write cycle timing is shown in Figure 3-7. BUS MASTER ADDRESS THE DEVICE 1) 2) 3) 4) 5) 6) PLACE FUNCTION CODE ON FC2-FC0 PLACE ADDRESS ON ADDRESS BUS ASSERT ADDRESS STROBE (AS) SET R/W TO WRITE PLACE DATA ON D15-D0 ASSERT UPPER DATA STROBE (UDS) AND LOWER DATA STROBE (LDS) SLAVE INPUT THE DATA 1) DECODE ADDRESS 2) LATCH DATA ON D15-D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE OUTPUT TRANSFER 1) 2) 3) 4) NEGATE UDS AND LDS NEGATE AS REMOVE DATA FROM D15-D0 SET R/W TO READ TERMINATE THE CYCLE 1) NEGATE DTACK START NEXT CYCLE Figure 3-5. Word Write Cycle Flowchart MOTOROLA MC68306 USER'S MANUAL 3-5 BUS MASTER ADDRESS THE DEVICE 1) 2) 3) 4) 5) PLACE FUNCTION CODE ON FC2-FC0 PLACE ADDRESS ON ADDRESS BUS ASSERT ADDRESS STROBE (AS) SET R/W TO WRITE PLACE DATA ON D0-D7 OR D15-D8 (ACCORDING TO INTERNAL A0) 6) ASSERT UPPER DATA STROBE (UDS) OR LOWER DATA STROBE (LDS) (BASED ON INTERNAL A0) TERMINATE OUTPUT TRANSFER 1) NEGATE UDS AND LDS 2) NEGATE AS 3) REMOVE DATA FROM D7-D0 OR D15-D8 4) SET R/W TO READ SLAVE INPUT THE DATA 1) DECODE ADDRESS 2) LATCH DATA ON D7-D0 IF LDS IS ASSERTED. LATCH DATA ON D15-D8 IF UDS IS ASSERTED 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE THE CYCLE 1) NEGATE DTACK START NEXT CYCLE Figure 3-6. Byte Write Cycle Flowchart S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 CLK FC2-FC0 A31-A1 A0* AS UDS LDS R/W DTACK D15-D8 D7-D0 *INTERNAL SIGNAL ONLY WORD WRITE ODD BYTE WRITE EVEN BYTE WRITE Figure 3-7. Word and Byte Write Cycle Timing Diagram 3-6 MC68306 USER'S MANUAL MOTOROLA The descriptions of the eight states of a write cycle are as follows: STATE 0 The write cycle starts in S0. The processor places valid function codes on FC2-FC0, a valid address on the address bus, and drives R/W high (if a preceding write cycle has left R/W low). During S1, no bus signals are altered. On the rising edge of S2, the processor asserts AS and drives R/W low. During S3, the data bus is driven out of the high-impedance state as the data to be written is placed on the bus. At the rising edge of S4, the processor asserts U D S and/or LDS;. The processor waits for a cycle termination signal (DTACK or BERR ). If neither termination signal is asserted before the falling edge at the end of S4, the processor inserts wait states (full clock cycles) until either DTACK or BERR is asserted. Case 1: DTACK received, with or without BERR . STATE 5 STATE 6 STATE 7 During S5, no bus signals are altered. During S6, no bus signals are altered. On the falling edge of the clock entering S7, the processor negates AS, UDS , and/or LDS . As the clock rises at the end of S7, the processor places the data bus in the high-impedance state, and drives R/W high. The device negates DTACK or BERR at this time. Case 2: BERR received without DTACK . STATE 5 STATE 6 STATE 7 STATE 8 STATE 9 During state 5 (S5), no bus signals are altered. During state 6 (S6), no bus signals are altered. During state 7 (S7), no bus signals are altered. During state 8 (S8), no bus signals are altered. AS and UDS/LDS negated. Slave negates BERR. At the end of S9, threestate data and drive R/W high. STATE 1 STATE 2 STATE 3 STATE 4 3.1.3 Read-Modify-Write Cycle The read-modify-write cycle performs a read operation, modifies the data in the arithmetic logic unit, and writes the data back to the same address. The address strobe ( AS) remains asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS) instruction uses this cycle to provide a signaling capability without deadlock between processors in a multiprocessing environment. The TAS instruction (the only instruction MOTOROLA MC68306 USER'S MANUAL 3-7 that uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write cycles are byte operations. The read-modify-write flowchart is shown in Figure 3-8 and the timing diagram is shown in Figure 3-9. BUS MASTER ADDRESS THE DEVICE 1) 2) 3) 4) 5) SET R/W TO READ PLACE FUNCTION CODE ON FC2-FC0 PLACE ADDRESS ON ADDRESS BUS ASSERT ADDRESS STROBE (AS) ASSERT UPPER DATA STROBE (UDS) OR LOWER DATA STROBE (LDS) SLAVE OUTPUT THE DATA 1) DECODE ADDRESS 2) PLACE DATA ON D7-D0 OR D15-D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) ACQUIRE THE DATA 1) LATCH DATA 1) NEGATE UDS AND LDS 2) START DATA MODIFICATION TERMINATE THE CYCLE 1) REMOVE DATA FROM D7-D0 OR D15-D8 2) NEGATE DTACK START OUTPUT TRANSFER 1) SET R/W TO WRITE 2) PLACE DATA ON D7-D0 OR D15-D8 3) ASSERT UPPER DATA STROBE (UDS) OR LOWER DATA STROBE (LDS) INPUT THE DATA 1) STORE DATA ON D7-D0 OR D15-D8 2) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE OUTPUT TRANSFER 1) NEGATE UDS OR LDS 2) NEGATE AS 3) REMOVE DATA FROM D7-D0 OR D15-D8 4) SET R/W TO READ TERMINATE THE CYCLE 1) NEGATE DTACK START NEXT CYCLE Figure 3-8. Read-Modify-Write Cycle Flowchart 3-8 MC68306 USER'S MANUAL MOTOROLA S0 S1 S2 S3 S4 S5 S6 CLK A31-A1 AS UDS OR LDS R/W DTACK D15-D8 OR D7-D0 FC2-FC0 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 INDIVISIBLE CYCLE Figure 3-9. Read-Modify-Write Cycle Timing Diagram The descriptions of the read-modify-write cycle states are as follows: STATE 0 The read cycle starts in S0. The processor places valid function codes on FC2-FC0, a valid address on the address bus, and drives R/W high to identify a read cycle. During S1, no bus signals are altered. On the rising edge of S2, the processor asserts AS and UDS /LDS. During S3, no bus signals are altered. During S4, the processor waits for a cycle termination signal (DTACK or BERR ). If neither termination signal is asserted before the falling edge at the end of S4, the processor inserts wait states (full clock cycles) until either DTACK or BERR is asserted. Case R1: DTACK only. STATE 5 STATE 6 STATE 7 During S5, no bus signals are altered. During S6, data from the device are driven onto the data bus. On the falling edge of the clock entering S7, the processor accepts data from the device and negates UDS /LDS . The device negates DTACK at this time. The bus signals are unaltered during S8-S11, during which the arithmetic logic unit makes appropriate modifications to the data. STATE 1 STATE 2 STATE 3 STATE 4 STATES 8-11 MOTOROLA MC68306 USER'S MANUAL 3-9 STATE 12 STATE 13 STATE 14 STATE 15 STATE 16 The write portion of the cycle starts in S12. The valid function codes on FC2-FC0, the address bus lines, AS, and R/W remain unaltered. During S13, no bus signals are altered. On the rising edge of S14, the processor drives R/W low. During S15, the data bus is driven out of the high-impedance state as the data to be written are placed on the bus. At the rising edge of S16, the processor asserts UDS /LDS . The processor waits for D T A C K or BERR . If neither termination signal is asserted before the falling edge at the close of S16, the processor inserts wait states (full clock cycles) until either DTACK or BERR is asserted. Case W1: DTACK with or without BERR . STATE 17 STATE 18 STATE 19 During S17, no bus signals are altered. During S18, no bus signals are altered. On the falling edge of the clock entering S19, the processor negates AS and UDS /LDS . As the clock rises at the end of S19, the processor places the data bus in the high-impedance state, and drives R/W high. The device negates DTACK or BERR at this time. Case R2: DTACK and BERR on read. STATE 5 STATE 6 STATE 7 During S5, no bus signals are altered. During S6, no bus signals are altered, and data from the device is ignored. AS and U D S /LDS are negated. The cycle terminates without the write portion. Case R3: BERR only on read. STATE 5 STATE 6 STATE 7 STATE 8 STATE 9 During S5, no bus signals are altered. During S6, no bus signals are altered.. During S7, no bus signals are altered. During S8, no bus signals are altered. AS and U D S /LDS are negated. The cycle terminates without the write portion. Case W2: BERR only on write. 3-10 MC68306 USER'S MANUAL MOTOROLA STATE 17 STATE 18 STATE 19 STATE 20 STATE 21 During S17, no bus signals are altered. During S18, no bus signals are altered. During S19, no bus signals are altered. During S20. no bus signals are altered. The processor negates AS and UDS /LDS. 3.1.4 CPU Space Cycle A CPU space cycle, indicated when the function codes are all high, is a special processor cycle. In the 68EC000 core, CPU space is used only for interrupt acknowledge cycles. Figure 3-10 shows the encoding of an interrupt acknowledge cycle. 31 INTERRUPT ACKNOWLEDGE 1 1 1 3 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL Figure 3-10. Interrupt Acknowledge Cycle The interrupt acknowledge cycle places the level of the interrupt being acknowledged on address bits A3-A1 and drives all other address lines high. The interrupt acknowledge cycle reads a vector number when the device places a vector number on the data bus. The timing diagram for an interrupt acknowledge cycle is shown in Figure 3-11. MOTOROLA MC68306 USER'S MANUAL 3-11 IPL2-IPL0 VALID INTERNALLY IPL2-IPL0 SAMPLED IPL2-IPL0 TRANSITION S0 S1 S2 S3 S4 S5 S6 S7 CLK FC2-FC0 A23-A4 A3-A1 AS S0 S1 S2 S3 S4 SW SW S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 UDS* LDS IACK R/W DTACK D15-D8 D7-D0 IPL2-IPL0 LAST BUS CYCLE OF INSTRUCTION (READ OR WRITE) STACK PCL (SSP) IACK CYCLE (VECTOR NUMBER ACQUISITION) STACK AND VECTOR FETCH The processor does not * Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. recognize anything on data lines D8 through D15 at this time. Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram 3.2 BUS ARBITRATION Bus arbitration is a technique used by bus master devices to request, to be granted, and to acknowledge bus mastership. Bus arbitration consists of the following: 1. Asserting a bus mastership request 2. Receiving a grant indicating that the bus is available at the end of the current cycle 3. Acknowledging that mastership has been assumed Figure 3-12 is a flowchart showing the bus arbitration cycle of the EC000 core. Figure 313 is a timing diagram of the bus arbitration cycle charted in Figure 3-12. This technique allows processing of bus requests during data transfer cycles. 3-12 MC68306 USER'S MANUAL MOTOROLA There are two ways to arbitrate the bus, 3-wire and 2-wire bus arbitration. The EC000 core can do either 2-wire or 3-wire bus arbitration. Figures 3-12 and 3-14 show 3-wire bus arbitration and Figures 3-13 and 5-15 show 2-wire bus arbitration. BGACK must be pulled high for 2-wire bus arbitration. PROCESSOR REQUESTING DEVICE REQUEST THE BUS 1) ASSERT BUS REQUEST (BR) GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE 3) NEXT BUS MASTER ASSERTS BUS GRANT ACKNOWLEDGE (BGACK) TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR TERMINATE ARBITRATION 1) NEGATE BG (AND WAIT FOR BGACK TO BE NEGATED) 2) IF BR REMAINS ASSERTED AFTER BGACK ASSERTED, RE-ASSERT BG. OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP REARBITRATE OR RESUME PROCESSOR OPERATION 1) NEGATE BGACK Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart MOTOROLA MC68306 USER'S MANUAL 3-13 PROCESSOR REQUESTING DEVICE REQUEST THE BUS 1) ASSERT BUS REQUEST (BR) GRANT BUS ARBITRATION 1) ASSERT BUS GRANT (BG) OPERATE AS BUS MASTER 1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE ACKNOWLEDGE RELEASE OF BUS MASTERSHIP 1) NEGATE BUS GRANT (BG) RELEASE BUS MASTERSHIP 1) NEGATE BUS REQUEST (BR) REARBITRATE OR RESUME PROCESSOR OPERATION Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart 3-14 MC68306 USER'S MANUAL MOTOROLA CLK FC2-FC0 A31-A1 AS LDS/ UDS R/W DTACK D15-D0 BR BG BGACK PROCESSOR DMA DEVICE PROCESSOR DMA DEVICE Figure 3-14. Three-Wire Bus Arbitration Timing Diagram S0 S2 S4 S6 CLK FC2-FC0 A19-A0 AS DS R/W DTACK D7-D0 BR BG PROCESSOR DMA DEVICE PROCESSOR DMA DEVICE S0 S2 S4 S6 S0 S2 S4 S6 S0 S2 S4 S6 Figure 3-15. Two-Wire Bus Arbitration Timing Diagram MOTOROLA MC68306 USER'S MANUAL 3-15 The timing diagram in Figure 3-14 shows that the bus request is negated at the time that an acknowledge is asserted. This type of operation applies to a system consisting of a processor and one other device capable of becoming bus master. In systems having several devices that can be bus masters, bus request lines from these devices can be wire-ORed at the processor, and more than one bus request signal could occur. The bus grant signal is negated a few clock cycles after the assertion of the bus grant acknowledge signal. However, if bus requests are pending, the processor reasserts bus grant for another request a few clock cycles after bus grant (for the previous request) is negated. In response to this additional assertion of bus grant, external arbitration circuitry selects the next bus master before the current bus master has completed the bus activity. The timing diagram in Figure 3-15 also applies to a system consisting of a processor and one other device capable of becoming bus master. Since the 2-wire bus arbitration scheme does not use a bus grant acknowledge signal, the external master must continue to assert BR until it has completed its bus activity. The processor negates bus grant when BR is negated. 3.2.1 Requesting the Bus External devices capable of becoming bus masters assert BR to request the bus. This signal can be wire-ORed (not necessarily constructed from open-collector devices) from any of the devices in the system that can become bus master. The processor, which is at a lower bus priority level than the external devices, relinquishes the bus after it completes the current bus cycle. 3.2.2 Receiving the Bus Grant The processor asserts BG as soon as possible. Normally, this process immediately follows internal synchronization, except when the processor has made an internal decision to execute the next bus cycle but has not yet asserted AS for that cycle. In this case, BG is delayed until AS is asserted to indicate to external devices that a bus cycle is in progress. BG can be routed through a daisy-chained network or through a specific priority-encoded network. Any method of external arbitration that observes the protocol can be used. 3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only) Upon receiving BG , the requesting device waits until AS, DTACK, and BGACK are negated before asserting BGACK. The negation of AS indicates that the previous bus master has completed its cycle. (No device is allowed to assume bus mastership while AS is asserted.) The negation of BGACK indicates that the previous master has released the bus. The negation of DTACK indicates that the previous slave has terminated the connection to the previous master. (In some applications, DTACK might not be included in this function; general-purpose devices would be connected using AS only.) When BGACK is asserted, the asserting device is bus master until it negates BGACK . BGACK should not be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus by negating BGACK . 3-16 MC68306 USER'S MANUAL MOTOROLA The bus request from the granted device should be negated after BGACK is asserted. If another bus request is pending, BG is reasserted within a few clocks, as described in 3.3 Bus Arbitration Control. The processor does not perform any external bus cycles before reasserting BG . 3.3 BUS ARBITRATION CONTROL All asynchronous bus arbitration signals to the processor are synchronized before being used internally. As shown in Figure 3-16, synchronization requires a maximum of one and a half cycles of the system clock. The input asynchronous signal is sampled on the falling edge of the clock and is valid internally after the next rising edge. This synchronization scheme is used for all other asynchronous inputs also: RESET, HALT, DTACK, BERR, IPL2-IPL0. INTERNAL SIGNAL VALID EXTERNAL SIGNAL SAMPLED CLK BR (EXTERNAL) 47 BR (iNTERNAL) Figure 3-16. External Asynchronous Signal Synchronization Bus arbitration control is implemented with a finite state machine (see Figure 3-17). In Figure 3-17, input signals R and A are the internally synchronized versions of BR and BGACK. The BG output is shown as G, and the internal three-state control signal is shown as T. If T is true, the address, data, and control buses are placed in the high-impedance state when AS is negated. All signals are shown in positive logic (active high), regardless of their true active voltage level. State changes (valid outputs) occur on the next rising edge of the clock after the internal signal is valid. A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 3-18. The bus arbitration timing while the bus is inactive (e.g., the processor is performing internal operations for a multiply instruction) is shown in Figure 3-19. MOTOROLA MC68306 USER'S MANUAL 3-17 When a bus request is made after the MPU has begun a bus cycle and before AS has been asserted (S0), the special sequence shown in Figure 3-20 applies. Instead of being asserted on the next rising edge of clock, BG is delayed until the second rising edge following its internal assertion. RA RA 1 GT XA 1 RA GT RA RA XX GT XA GT RA RA RA GT RA RA GT R+A RX GT XX RA (a) 3-Wire Bus Arbitration R R GT STATE 0 R GT STATE 1 X R GT STATE 4 GT STATE 3 GT STATE 2 R X R R = Bus Request Internal A = Bus Grant Acknowledge Internal G = Bus Grant T = Three-state Control to Bus Control Logic X = Don't Care (b) 2-Wire Bus Arbitration Notes: 1. State machine will not change if the bus is S0 or S1. Refer to BUS ARBITRATION CONTROL. 5.2.3. 2. The address bus will be placed in the high-impedance state if T is asserted and AS is negated. Figure 3-17. Bus Arbitration Unit State Diagrams 3-18 MC68306 USER'S MANUAL MOTOROLA Figures 3-18, 3-19, and 3-20 apply to processors using 3-wire bus arbitration. Figures 3-21, 3-22, and 3-23 apply to processors using 2-wire bus arbitration. BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK S0 S1 S2 S3 S4 S5 S6 S7 BR BG BGACK FC2-FC0 A31-A1 AS UDS LDS R/W S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED INTERNAL BGACK SAMPLED BGACK NEGATED DTACK D15-D0 PROCESSOR ALTERNATE BUS MASTER PROCESSOR Figure 3-18. Three-Wire Bus Arbitration Timing Diagram--Processor Active MOTOROLA MC68306 USER'S MANUAL 3-19 BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK S0 S1 S2 S3 S4 S5 S6 S7 BR BG BGACK FC2-FC0 A31-A1 AS UDS LDS R/W DTACK D15-D0 PROCESSOR BUS INACTIVE ALTERNATE BUS MASTER PROCESSOR S0 S1 S2 S3 S4 Figure 3-19. Three-Wire Bus Arbitration Timing Diagram--Bus Inactive 3-20 MC68306 USER'S MANUAL MOTOROLA BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED INTERNAL BGACK SAMPLED BGACK NEGATED CLK S0 BR BG BGACK FC2-FC0 A31-A1 AS UDS LDS R/W S2 S4 S6 S0 S2 S4 S6 S0 DTACK D15-D0 PROCESSOR ALTERNATE BUS MASTER PROCESSOR Figure 3-20. Three-Wire Bus Arbitration Timing Diagram--Special Case MOTOROLA MC68306 USER'S MANUAL 3-21 BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK S0 S1 S2 S3 S4 S5 S6 S7 BR BG BGACK FC2-FC0 A31-A1 AS UDS LDS R/W BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED INTERNAL BR SAMPLED BR NEGATED S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 DTACK D15-D0 PROCESSOR ALTERNATE BUS MASTER PROCESSOR Figure 3-21. Two-Wire Bus Arbitration Timing Diagram--Processor Active 3-22 MC68306 USER'S MANUAL MOTOROLA BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED BG ASSERTED AND BUS THREE STATED BR VALID INTERNAL BR SAMPLED BR ASSERTED CLK S0 S1 S2 S3 S4 S5 S6 S7 BR BG BGACK FC2-FC0 A31-A1 AS UDS LDS R/W DTACK D15-D0 PROCESSOR BUS INACTIVE ALTERNATE BUS MASTER PROCESSOR S0 S1 S2 S3 S4 Figure 3-22. Two-Wire Bus Arbitration Timing Diagram--Bus Inactive MOTOROLA MC68306 USER'S MANUAL 3-23 BUS THREE-STATED BG ASSERTED BR VALID INTERNAL BR SAMPLED BR ASSERTED BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED INTERNAL BR SAMPLED BR NEGATED CLK S0 BR BG BGACK FC2-FC0 A31-A1 AS UDS LDS R/W S2 S4 S6 S0 S2 S4 S6 S0 DTACK D15-D0 PROCESSOR ALTERNATE BUS MASTER PROCESSOR Figure 3-23. Two-Wire Bus Arbitration Timing Diagram--Special Case 3.4 BUS ERROR AND HALT OPERATION In a bus architecture that requires a handshake from an external device, such as the asynchronous bus used in the M68000 Family, the handshake may not always occur. A bus error input is provided to terminate a bus cycle in error when the expected signal is not asserted. Different systems and different devices within the same system require different maximum-response times. External circuitry can be provided to assert the bus error signal after the appropriate delay following the assertion of address strobe. 3.4.1 Bus Error Operation A bus error is recognized when BERR is asserted, HALT is negated, and DTACK is not asserted before BERR (or not at all). When the bus error condition is recognized, the current bus cycle is terminated in S7 (DTACK and BERR together) or S9 (BERR alone) for a read cycle, a write cycle, or the read portion of a read-modify-write cycle. For the write portion of a read-modify-write cycle, the current bus cycle is terminated in S19 (DTACK and BERR together) or S21 3-24 MC68306 USER'S MANUAL MOTOROLA (BERR alone). As long as BERR remains asserted, the data bus is in the high-impedance state. Figure 3-24 shows the timing for the normal bus error. S0 CLK FC2-FC0 A31-A1 AS LDS/UDS R/W DTACK S2 S4 w w w w S6 S8 D15-D0 BERR HALT INITIATE READ RESPONSE FAILURE BUS ERROR DETECTION INITIATE BUS ERROR STACKING Figure 3-24. Bus Error Timing Diagram After the aborted bus cycle is terminated and BERR is negated, the processor enters exception processing for the bus error exception. During the exception processing sequence, the following information is placed on the supervisor stack: 1. Status register 2. Program counter (two words, which may be up to five words past the instruction being executed) 3. Error information The first two items are identical to the information stacked by any other exception. The EC000 core stacks bus error information to help determine and to correct the error. After the processor has placed the required information on the stack, the bus error exception vector is read from vector table entry 2 (offset $08) and placed in the program counter. The processor resumes execution at the address in the vector, which is the first instruction in the bus error handler routine. 3.4.2 Retrying the Bus Cycle The assertion of the bus error signal during a bus cycle in which HALT is also asserted by an external device initiates a retry operation. Figure 3-25 is a timing diagram of the retry operation. MOTOROLA MC68306 USER'S MANUAL 3-25 S0 CLK FC2-FC0 A23-A1 AS LDS/UDS R/W DTACK D15-D0 BERR HALT S2 S4 S6 S8 S0 S2 S4 S6 1 CLOCK PERIOD READ HALT RETRY Figure 3-25. Retry Bus Cycle Timing Diagram The processor terminates the bus cycle, and remains in this state until HALT is negated. Then the processor retries the preceding cycle using the same function codes, address, and data (for a write operation). BERR should be negated at least one clock cycle before HALT is negated. NOTE To guarantee that the entire read-modify-write cycle runs correctly and that the write portion of the operation is performed without negating the address strobe, the processor does not retry a read-modify-write cycle. When BERR occurs during a read-modify-write operation, a bus error operation is performed whether or not HALT is asserted. 3.4.3 Halt Operation HALT performs a halt/run/single-step operation. When HALT is asserted by an external device, the processor halts and remains halted as long as the signal remains asserted, as shown in Figure 3-26. While the processor is halted, bus arbitration is performed as usual. Should a bus error occur while HALT is asserted, the processor performs the retry operation previously described. NOTE If a RESET instruction is executed while HALT is asserted, the CPU will be reset. 3-26 MC68306 USER'S MANUAL MOTOROLA S0 CLK FC2-FC0 A31-A1 AS LDS/UDS R/W DTACK D15-D0 HALT S2 S4 S6 S0 S2 S4 S6 READ HALT READ Figure 3-26. Halt Operation Timing Diagram The single-step mode is derived from correctly timed transitions of HALT. HALT is negated to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the cycle completes. The single-step mode proceeds through a program one bus cycle at a time for debugging purposes. The halt operation and the hardware trace capability allow tracing of either bus cycles or instructions one at a time. These capabilities and a software debugging package provide total debugging flexibility. 3.4.4 Double Bus Fault When a bus error exception occurs, the processor begins exception processing by stacking information on the supervisor stack. If another bus error occurs during exception processing (i.e., before execution of another instruction begins) the processor halts and asserts HALT. This is called a double bus fault. Only an external reset operation can restart a processor halted due to a double bus fault. A retry operation does not initiate exception processing; a bus error during a retry operation does not cause a double bus fault. The processor can continue to retry a bus cycle indefinitely if external hardware requests. A double bus fault occurs during a reset operation when a bus error occurs while the processor is reading the vector table (before the first instruction is executed). The reset operation is described in the following paragraph. 3.5 RESET OPERATION RESET is asserted externally for the initial processor reset. Subsequently, the signal can be asserted either externally or internally (executing a RESET instruction). MOTOROLA MC68306 USER'S MANUAL 3-27 After the processor is reset, it reads the reset vector table entry (address $00000) and loads the contents into the supervisor stack pointer (SSP). Next, the processor loads the contents of address $00004 (vector table entry 1) into the program counter. Then the processor initializes the interrupt level in the status register to a value of seven. No other register is affected by the reset sequence. Figure 3-27 shows the timing of the reset operation. CLK + 5 VOLTS VCC RESET T 100 MILLISECONDS HALT T < 4 CLOCKS BUS CYCLES 2 NOTES: 1. Internal start-up time 2. SSP high read in here 3. SSP low read in here 4. PC High read in here 5. PC Low read in here 6. First instruction fetched here Bus State Unknown: All Control Signals Inactive. Data Bus in Read Mode: 3 4 5 6 1 Figure 3-27. Reset Operation Timing Diagram The active-low RESET signal is asserted by the EC000 core when a RESET instruction is executed. This signal should reset all external devices (the EC000 core itself is not affected). The processor drives RESET for 124 clock periods. The RESET signal is asserted by an external source to reset the EC000 core. RESET by itself will reset the EC000 core unless the processor is executing a RESET instruction. To guarantee a reset of the core, RESET must be asserted for at least 132 clocks (i.e., longer than the maximum duration of the RESET instruction), or RESET and HALT must be asserted together for at least 10 clocks. 3.6 THE RELATIONSHIP OF DTACK, BERR, AND HALT To properly control termination of a bus cycle for a retry or a bus error condition, DTACK, BERR , and HALT should be asserted and negated on the rising edge of the processor clock. This relationship assures that when two signals are asserted simultaneously, the required setup time (specification #47, AC Electrical SpecificationsNRead and Write Cycles) for both of them is met during the same bus state. External circuitry should be designed to incorporate this precaution. A related specification, #48, can be ignored when DTACK, BERR , and HALT are asserted and negated on the rising edge of the processor clock. 3-28 MC68306 USER'S MANUAL MOTOROLA The possible bus cycle terminations can be summarized as follows (case numbers refer to Table 3-1). Normal Termination: Halt Termination: DTACK is asserted. BERR and HALT remain negated (case 1). HALT is asserted coincident with or preceding DTACK, and BERR remains negated (case 2). Bus Error Termination: BERR is asserted in lieu of, coincident with, or preceding DTACK (case 3). Retry Termination: HALT and BERR asserted in lieu of, coincident with, or before DTACK (case 5). Table 3-1 shows the details of the resulting bus cycle terminations for various combinations of signal sequences. Table 3-1. Case No. Control Signal DTACK, BERR , and HALT Assertion Results Asserted on Rising Edge of State N N+2 S NA X S NA S X S NA S A NA X S S S A A Normal cycle terminate and continue. EC000 Core Results 1 DTACK BERR HALT DTACK BERR HALT DTACK BERR HALT DTACK BERR HALT DTACK BERR HALT DTACK BERR HALT -- -- -- -- -- A NA NA A NA A/S X A NA A NA NA X A A/S A NA NA 2 Normal cycle terminate and halt. Continue when HALT negated. Terminate and take bus error trap. 3 4 Normal cycle terminate and continue. 5 Terminate and retry when HALT removed. 6 Normal cycle terminate and continue. LEGEND: N A NA X S The number of the current even bus state (e.g., S4, S6, etc.) Signal asserted in this bus state Signal not asserted in this bus state Don't care Signal asserted in preceding bus state and remains asserted in this state NOTE: All operations are subject to relevant setup and hold times. MOTOROLA MC68306 USER'S MANUAL 3-29 The negation of BERR and HALT under several conditions is shown in Table 3-2. (DTACK is assumed to be negated normally in all cases; for reliable operation, both DTACK and BERR should be negated when address strobe is negated). EXAMPLE A: A system uses a watchdog timer to terminate accesses to unused address space. The timer asserts BERR after timeout (case 3). EXAMPLE B: A system uses error detection on random-access memory (RAM) contents. The system designer may: 1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT simultaneously to retry the error cycle (case 5). 2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same time as DTACK (case 3). Table 3-2. Conditions of Termination in Table 4-4 Bus Error Rerun Rerun Normal Normal Control Signal BERR HALT BERR HALT BERR HALT BERR HALT BERR HALT BERR N * * * * * and HALT Negation Results N+2 Results--Next Cycle Takes bus error trap. Illegal sequence; usually traps to vector number 0. Reruns the bus cycle. * May lengthen next cycle. Negated on Rising Edge of State or or or * * * * * * or or * * none If next cycle is started, it will be terminated as a bus error. * = Signal is negated in this bus state. 3.7 ASYNCHRONOUS OPERATION To achieve clock frequency independence at a system level, the bus can be operated in an asynchronous manner. Asynchronous bus operation uses the bus handshake signals to control the transfer of data. The handshake signals are AS, UDS, LDS , DTACK, BERR , and HALT. AS indicates the start of the bus cycle, and UDS and LDS signal valid data for a write cycle. After placing the requested data on the data bus (read cycle) or latching the data (write cycle), the slave device (memory or peripheral) asserts DTACK to terminate the bus cycle. If no device responds or if the access is invalid, external control logic asserts BERR , or BERR and HALT, to abort or retry the cycle. Figure 3-28 shows the use of the bus handshake signals in a fully asynchronous read cycle. Figure 3-29 shows a fully asynchronous write cycle. 3-30 MC68306 USER'S MANUAL MOTOROLA ADDR AS R/W UDS/LDS DATA DTACK Figure 3-28 Fully Asynchronous Read Cycle ADDR AS R/W UDS/LDS DATA DTACK Figure 3-29. Fully Asynchronous Write Cycle In the asynchronous mode, the accessed device operates independently of the frequency and phase of the system clock. For example, the MC68681 dual universal asynchronous receiver/transmitter (DUART) does not require any clock-related information from the bus master during a bus transfer. Asynchronous devices are designed to operate correctly with processors at any clock frequency when relevant timing requirements are observed. A device can use a clock at the same frequency as the system clock (e.g., 8, 10, or 12.5 MHz), but without a defined phase relationship to the system clock. This mode of operation is pseudo-asynchronous; it increases performance by observing timing parameters related to the system clock frequency without being completely synchronous with that clock. A memory array designed to operate with a particular frequency processor but not driven by the processor clock is a common example of a pseudo-asynchronous device. The designer of a fully asynchronous system can make no assumptions about address setup time, which could be used to improve performance. With the system clock frequency known, the slave device can be designed to decode the address bus before recognizing an address strobe. Parameter #11 (refer to AC Electrical Specifications--Read and Write Cycles) specifies the minimum time before address strobe during which the address is valid. MOTOROLA MC68306 USER'S MANUAL 3-31 In a pseudo-asynchronous system, timing specifications allow DTACK to be asserted for a read cycle before the data from a slave device is valid. The length of time that DTACK may precede data is specified as parameter #31. This parameter must be met to ensure the validity of the data latched into the processor. No maximum time is specified from the assertion of AS to the assertion of DTACK. During this unlimited time, the processor inserts wait cycles in one-clock-period increments until DTACK is recognized. Figure 3-30 shows the important timing parameters for a pseudo-asynchronous read cycle. ADDR 11 AS 17 R/W UDS/LDS 28 A DATA 31 DTACK 29 Figure 3-30. Pseudo-Asynchronous Read Cycle During a write cycle, after the processor asserts AS but before driving the data bus, the processor drives R/W low. Parameter #55 specifies the minimum time between the transition of R/W and the driving of the data bus, which is effectively the maximum turnoff time for any device driving the data bus. After the processor places valid data on the bus, it asserts the data strobe signal(s). A data setup time, similar to the address setup time previously discussed, can be used to improve performance. Parameter #26 is the minimum time a slave device can accept valid data before recognizing a data strobe. The slave device asserts DTACK after it accepts the data. Parameter #25 is the minimum time after negation of the strobes during which the valid data remains on the address bus. Parameter #28 is the maximum time between the negation of the strobes by the processor and the negation of DTACK by the slave device. If DTACK remains asserted past the time specified by parameter #28, the processor may recognize it as being asserted early in the next bus cycle and may terminate that cycle prematurely. Figure 3-31 shows the important timing specifications for a pseudo-asynchronous write cycle. 3-32 MC68306 USER'S MANUAL MOTOROLA ADDR 11 AS 20A R/W 22 UDS/LDS 55 DATA C DTACK 26 28 29 Figure 3-31. Pseudo-Asynchronous Write Cycle 3.8 SYNCHRONOUS OPERATION In some systems, external devices use the system clock to generate DTACK and other asynchronous input signals. This synchronous operation provides a closely coupled design with maximum performance, appropriate for frequently accessed parts of the system. For example, memory can operate in the synchronous mode, but peripheral devices operate asynchronously. For a synchronous device, the designer uses explicit timing information shown in AC Electrical Specifications--Read and Write Cycles. These specifications define the state of all bus signals relative to a specific state of the processor clock. The standard M68000 bus cycle consists of four clock periods (eight bus cycle states) and, optionally, an integral number of clock cycles inserted as wait states. Wait states are inserted as required to allow sufficient response time for the external device. The following state-by-state description of the bus cycle differs from those descriptions in 3.1.1 Read Cycle and 3.1.2 Write Cycle by including information about the important timing parameters that apply in the bus cycle states. STATE 0 The bus cycle starts in S0, during which the clock is high. At the rising edge of S0, the function code for the access is driven externally. Parameter #6A defines the delay from this rising edge until the function codes are valid. Also, the R/W signal is driven high; parameter #18 defines the delay from the same rising edge to the transition of R/W . The minimum value for parameter #18 applies to a read cycle preceded by a write cycle; this value is the maximum hold time for a low on R/W beyond the initiation of the read cycle. MOTOROLA MC68306 USER'S MANUAL 3-33 STATE 1 STATE 2 Entering S1, a low period of the clock, the address of the accessed device is driven externally with an assertion delay defined by parameter #6. On the rising edge of S2, a high period of the clock, AS is asserted. During a read cycle, UDS and/or LDS is also asserted at this time. Parameter #9 defines the assertion delay for these signals. For a write cycle, the R/W signal is driven low with a delay defined by parameter #20. On the falling edge of the clock entering S3, the data bus is driven out of the high-impedance state with the data being written to the accessed device (in a write cycle). Parameter #23 specifies the data assertion delay. In a read cycle, no signal is altered in S3. Entering the high clock period of S4, U D S /LDS is asserted (during a write cycle) on the rising edge of the clock. As in S2 for a read cycle, parameter #9 defines the assertion delay from the rising edge of S4 for U D S /LDS . In a read cycle, no signal is altered by the processor during S4. Until the falling edge of the clock at the end of S4 (beginning of S5), no response from any external device except RESET is acknowledged by the processor. If either DTACK or BERR is asserted before the falling edge of S4 and satisfies the input setup time defined by parameter #47, the processor enters S5 and the bus cycle continues. If either DTACK or BERR is asserted but without meeting the setup time defined by parameter #47, the processor may recognize the signal and continue the bus cycle; the result is unpredictable. If neither DTACK nor BERR is asserted before the next rise of clock, the bus cycle remains in S4, and wait states (complete clock cycles) are inserted until one of the bus cycle terminations is met. STATE 3 STATE 4 STATE 5 STATE 6 S5 is a low period of the clock, during which the processor does not alter any signal. S6 is a high period of the clock, during which data for a read operation is set up relative to the falling edge (entering S7). Parameter #27 defines the minimum period by which the data must precede the falling edge. For a write operation, the processor changes no signal during S6. On the falling edge of the clock entering S7, the processor latches data and negates A S and UDS/ LDS during a read cycle. The hold time for these strobes from this falling edge is specified by parameter #12. The hold time for data relative to the negation of A S and U D S /LDS is specified by parameter #29. For a write cycle, only AS and UDS /LDS , are negated; timing parameter #12 also applies. STATE 7 3-34 MC68306 USER'S MANUAL MOTOROLA On the rising edge of the clock, at the end of S7 (which may be the start of S0 for the next bus cycle), the processor places the address bus in the high-impedance state. During a write cycle, the processor also places the data bus in the high-impedance state and drives R/W high. External logic circuitry should respond to the negation of the AS and UDS /LDS by negating DTACK and/or BERR . Parameter #28 is the hold time for DTACK, and parameter #30 is the hold time for BERR . Figure 3-32 shows a synchronous read cycle and the important timing parameters that apply. The timing for a synchronous read cycle, including relevant timing parameters, is shown in Figure 3-33. S0 CLOCK 6 ADDR 9 AS S1 S2 S3 S4 S5 S6 S7 S0 UDS/LDS 18 R/W 47 DTACK 27 DATA Figure 3-32. Synchronous Read Cycle MOTOROLA MC68306 USER'S MANUAL 3-35 S0 CLOCK 6 ADDR S1 S2 S3 S4 S5 S6 S7 S0 9 AS UDS/LDS 18 R/W 47 DTACK 23 DATA 53 Figure 3-33. Synchronous Write Cycle A key consideration when designing in a synchronous environment is the timing for the assertion of DTACK and BERR by an external device. To properly use external inputs, the processor must synchronize these signals to the internal clock. The processor must sample the external signal, which has no defined phase relationship to the CPU clock, which may be changing at sampling time, and must determine whether to consider the signal high or low during the succeeding clock period. Successful synchronization requires that the internal machine receives a valid logic level, whether the input is high, low, or in transition. Parameter #47 of AC Electrical Specifications--Read and Write Cycles is the asynchronous input setup time. Signals that meet parameter #47 are guaranteed to be recognized at the next falling edge of the system clock. However, signals that do not meet parameter #47 are not guaranteed to be recognized. In addition, if DTACK is recognized on a falling edge, valid data is latched into the processor (during a read cycle) on the next falling edge, provided the data meets the setup time required (parameter #27). When parameter #27 has been met, parameter #31 may be ignored. If DTACK is asserted with the required setup time before the falling edge of S4, no wait states are incurred, and the bus cycle runs at its maximum speed of four clock periods. 3-36 MC68306 USER'S MANUAL MOTOROLA SECTION 4 EC000 CORE PROCESSOR The EC000 core has a 16-bit data bus and 32-bit address bus while the full architecture provides for 32-bit address and data register operations. 4.1 FEATURES The following resources are available to the EC000 core: * 8 32-Bit Address Registers * 8 32-Bit Data Registers * 4-Gbyte Direct Addressing Range * 56 Powerful Instructions * Operations on Five Main Data Types * Memory-Mapped Input/Output (I/O) * 14 Addressing Modes 4.2 PROCESSING STATES The processor is always in one of three states: normal processing, exception processing, or halted. It is in the normal processing state when executing instructions, fetching instructions and operands, and storing instruction results. Exception processing is the transition from program processing to system, interrupt, and exception handling. Exception processing includes fetching the exception vector, stacking operations, and refilling the instruction pipe after an exception. The processor enters exception processing when an exceptional internal condition arises such as tracing an instruction, an instruction results in a trap, or executing specific instructions. External conditions, such as interrupts and access errors, also cause exceptions. Exception processing ends when the first instruction of the exception handler begins to execute. The processor halts when it receives an access error or generates an address error while in the exception processing state. For example, if during exception processing of one access error another access error occurs, the processor is unable to complete the transition to normal processing and cannot save the internal state of the machine. The processor assumes that the system is not operational and halts. Only an external reset can restart a halted processor. Note that when the processor executes a STOP instruction, it is in a special type of normal processing state, one without bus cycles. The processor stops, but it does not halt. MOTOROLA MC68306 USER'S MANUAL 4-1 4.3 PROGRAMMING MODEL The EC000 core executes instructions in one of two modes--user mode or supervisor mode. The user mode provides the execution environment for the majority of application programs. The supervisor mode, which allows some additional instructions and privileges, is used by the operating system and other system software. To provide upward compatibility of code written for a specific implementation of the EC000 core, the user programmer's model, illustrated in Figure 4-1, is common to all implementations. In the user programmer's model, the EC000 core offers 16, 32-bit, general-purpose registers (D0-D7, A0-A7), a 32-bit program counter, and an 8-bit condition code register. The first eight registers (D0-D7) are used as data registers for byte (8-bit), word (16-bit), and long-word (32-bit) operations. The second set of seven registers (A0-A6) and the user stack pointer (USP) can be used as software stack pointers and base address registers. In addition, the address registers can be used for word and long-word operations. All of the 16 registers can be used as index registers. The supervisor programmer's model consists of supplementary registers used in the supervisor mode. 31 0 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7/USP PC CCR DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER USER PROGRAMMING MODEL 31 0 SSP (CCR) SR SUPERVISOR STACK POINTER STATUS REGISTER (CCR IS ALSO SHOWN IN THE USER PROGRAMMING MODEL) SUPERVISOR PROGRAMMING MODEL EC1 Figure 4-1. Programmer's Model 4-2 MC68306 USER'S MANUAL MOTOROLA The status register, illustrated in Figure 4-2, contains the interrupt mask (eight levels available) and the following condition codes: overflow (V), zero (Z), negative (N), carry (C), and extend (X). Additional status bits indicate that the processor is in the trace (T) mode and/or in the supervisor (S) state. USER BYTE (CONDITION CODE REGISTER) SYSTEM BYTE 15 T 14 0 13 S 12 0 11 0 10 I2 9 I1 8 I0 7 0 6 0 5 0 4 X 3 N 2 Z 1 V 0 C TRACE MODE SUPERVISOR/USER STATE INTERRUPT PRIORITY MASK EXTEND NEGATIVE ZERO OVERFLOW CARRY EC2 Figure 4-2. Status Register 4.3.1 Data Format Summary The processor supports the basic data formats of the M68000 family. The instruction set supports operations on other data formats such as memory addresses. The operand data formats supported by the integer unit (IU) are the standard twoscomplement data formats defined in the M68000 family architecture. Registers, memory, or instructions themselves can contain IU operands. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Table 4-1 lists the data formats for the processor. Refer to M68000PM/AD, M68000 Family Programmer's Reference Manual, for details on data format organization in registers and memory. Table 4-1. Processor Data Formats Operand Data Format Bit Binary-Coded Decimal (BCD) Byte Integer Word Integer Long-Word Integer Size 1 Bit 8 Bits 8 Bits 16 Bits 32 Bits -- Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte -- -- -- Notes MOTOROLA MC68306 USER'S MANUAL 4-3 4.3.2 Addressing Capabilities Summary The EC000 core supports the basic addressing modes of the M68000 family. The register indirect addressing modes support postincrement, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated applications and high-level languages. The program counter indirect mode also has indexing and offset capabilities. This addressing mode is typically required to support position-independent software. Besides these addressing modes, the processor provides index sizing and scaling features. An instruction's addressing mode can specify the value of an operand, a register containing the operand, or how to derive the effective address of an operand in memory. Each addressing mode has an assembler syntax. Some instructions imply the addressing mode for an operand. These instructions include the appropriate fields for operands that use only one addressing mode. Table 4-2 lists a summary of the effective addressing modes for the processor. Refer to M68000PM/AD, M68000 Family Programmer's Reference Manual, for details on instruction format and addressing modes. Table 4-2. Effective Addressing Modes Addressing Modes Register Direct Addressing Data Register Direct Address Register Direct Absolute Data Addressing Absolute Short Absolute Long EA=Dn EA=An EA=(Next Word) EA=(Next Two Words) Syntax Program Counter Relative Addressing Relative with Offset EA=(PC)+d16 Relative with Index and Offset EA=(PC)+d8 Register Indirect Addressing Register Indirect Postincrement Register Indirect Predecrement Register Indirect Register Indirect with Offset Indexed Register Indirect with Offset Immediate Data Addressing Immediate Quick Immediate Implied Addressing Implied Register EA=(An) EA=(An), An An+N An An-N, EA=(An) EA=(An)+d 16 EA=(An)+(Xn)+d 8 DATA=Next Word(s) Inherent Data EA=SR, USP, SSP, PC, VBR, SFC, DFC 4-4 MC68306 USER'S MANUAL MOTOROLA 4.3.3 Notation Conventions Table 4-3 lists the notation conventions used in this manual unless otherwise specified. Table 4-3. Notation Conventions Single and Double Operand Operations + - x / ~ V tested sign-extended Arithmetic addition or postincrement indicator. Arithmetic subtraction or predecrement indicator. Arithmetic multiplication. Arithmetic division or conjunction symbol. Invert; operand is logically complemented. Logical AND Logical OR Logical exclusive OR Source operand is moved to destination operand. Two operands are exchanged. Any double-operand operation. Operand is compared to zero and the condition codes are set appropriately. All bits of the upper portion are made equal to the high-order bit of the lower portion. Other Operations TRAP STOP 10 If then else Equivalent to Format / Offset Word (SSP); SSP - 2 SSP; PC (SSP); SSP - 4 SSP; SR (SSP); SSP - 2 SSP; (Vector) PC Enter the stopped state, waiting for interrupts. The operand is BCD; operations are performed in decimal. Test the condition. If true, the operations after "then" are performed. If the condition is false and the optional "else" clause is present, the operations after "else" are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. Register Specification An Ax, Ay BR Dc Dh, Dl Dn Dr, Dq Du Dx, Dy Rn Rx, Ry Xn Any Address Register n (example: A3 is address register 3) Source and destination address registers, respectively. Base Register--An, PC, or suppressed. Data register D7-D0, used during compare. Data registers high- or low-order 32 bits of product. Any Data Register n (example: D5 is data register 5) Data register's remainder or quotient of divide. Data register D7-D0, used during update. Source and destination data registers, respectively. Any Address or Data Register Any source and destination registers, respectively. Index Register--An, Dn, or suppressed. MOTOROLA MC68306 USER'S MANUAL 4-5 Table 4-3. Notation Conventions (Continued) Data Format And Type B, W, L k Operand Data Format: Byte (B), Word (W), Long (L), or Packed (P). Specifies a signed integer data type (twos complement) of byte, word, or long word. A twos complement signed integer (-64 to +17) specifying a number's format to be stored in the packed decimal format. Subfields and Qualifiers # or # () [] bd dn LSB LSW MSB MSW od SCALE SIZE {offset:width} Immediate data following the instruction word(s). Identifies an indirect address in a register. Identifies an indirect address in memory. Base Displacement Displacement Value, n Bits Wide (example: d16 is a 16-bit displacement). Least Significant Bit Least Significant Word Most Significant Bit Most Significant Word Outer Displacement A scale factor (1, 2, 4, or 8, for no-word, word, long-word, or quad-word scaling, respectively). The index register's size (W for word, L for long word). Bit field selection. Register Names CCR PC SR Condition Code Register (lower byte of status register) Program Counter Status Register 4-6 MC68306 USER'S MANUAL MOTOROLA Table 4-3. Notation Conventions (Concluded) Register Codes * C cc FC N U V X Z -- General Case. Carry Bit in CCR Condition Codes from CCR Function Code Negative Bit in CCR Undefined, Reserved for Motorola Use. Overflow Bit in CCR Extend Bit in CCR Zero Bit in CCR Not Affected or Applicable. Stack Pointers SP SSP USP Active Stack Pointer Supervisor Stack Pointer User Stack Pointer Miscellaneous
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